Design and implementation of an out of order execution engine of floating point arithmetic operations
In this thesis, work is undertaken towards the design in hardware description languages and implementation in FPGA of an out of order execution engine of floating point arithmetic operations. This thesis work, is part of a project called Lagarto.
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2016 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/82655 |
| Acceso en línea: | https://hdl.handle.net/2117/82655 |
| Access Level: | acceso abierto |
| Palabra clave: | Field programmable gate arrays FP Engine IEEE 754 Standard Dynamic scheduling High performance techniques Low power consumption techniques Issue Queue Out of Order processors Superscalar processors. Matrius de portes programables in situ Àrees temàtiques de la UPC::Informàtica |
| Sumario: | In this thesis, work is undertaken towards the design in hardware description languages and implementation in FPGA of an out of order execution engine of floating point arithmetic operations. This thesis work, is part of a project called Lagarto. |
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