A Reorder Buffer Design for High Performance Processors
Modern reorder buffers (ROBs) were conceived to improve processor performance by allowing instruction execution out of the original program order and run ahead of sequential instruction code exploiting existing instruction level parallelism (ILP). The ROB is a functional structure of a processor exe...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2012 |
| País: | México |
| Institución: | Instituto Politécnico Nacional |
| Repositorio: | Redalyc-IPN |
| OAI Identifier: | oai:redalyc.org:61523304003 |
| Acceso en línea: | https://www.redalyc.org/articulo.oa?id=61523304003 |
| Access Level: | acceso abierto |
| Palabra clave: | Computación buffer reorder instruction window low power consumption Superscalar processors |
| Sumario: | Modern reorder buffers (ROBs) were conceived to improve processor performance by allowing instruction execution out of the original program order and run ahead of sequential instruction code exploiting existing instruction level parallelism (ILP). The ROB is a functional structure of a processor execution engine that supports speculative execution, physical register recycling, and precise exception recovering. Traditionally, the ROB is considered as a monolithic circular buffer with incoming instructions at the tail pointer after the decoding stage and completing instructions at the head pointer after the commitment stage. The latter stage verifies instructions that have been dispatched, issued, executed, and are not completed speculatively. This paper presents a design of distributed reorder buffer microarchitecture by using small structures near building blocks which work together, using the same tail and head pointer values on all structures for synchronization. The reduction of area, and therefore, the reduction of power and delay make this design suitable for both embedded and high performance microprocessors. |
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