Pre-silicon FEC decoding verification on SoC FPGAs

Forward error correction (FEC) decoding hardware modules are challenging to verify at pre-silicon stage, when they are usually described at register-transfer (RT)/logic level with a hardware description language (HDL). They tend to hide faults due to their inherent tendency to correct errors and the...

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Autores: Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X, Abad García, Carlos, Álvarez Ruiz, Ángel, Ugarte Olano, Íñigo, Sánchez Espeso, Pablo Pedro
Tipo de recurso: artículo
Fecha de publicación:2021
País:España
Institución:Universidad de Cantabria (UC)
Repositorio:UCrea Repositorio Abierto de la Universidad de Cantabria
Idioma:inglés
OAI Identifier:oai:repositorio.unican.es:10902/20523
Acceso en línea:http://hdl.handle.net/10902/20523
Access Level:acceso abierto
Palabra clave:Verification
Platform FPGAs
Prototyping
Emulation
BER/CER testing
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spelling Pre-silicon FEC decoding verification on SoC FPGAsFernández Solórzano, Víctor Manuel|||0000-0003-0614-151XAbad García, CarlosÁlvarez Ruiz, ÁngelUgarte Olano, ÍñigoSánchez Espeso, Pablo PedroVerificationPlatform FPGAsPrototypingEmulationBER/CER testingForward error correction (FEC) decoding hardware modules are challenging to verify at pre-silicon stage, when they are usually described at register-transfer (RT)/logic level with a hardware description language (HDL). They tend to hide faults due to their inherent tendency to correct errors and the required simulations with a massive insertion of inputs are too slow. In this work, two verification techniques based on FPGA-prototyping are applied in order to complement the mentioned simulations: golden model vs implementation matching with thousands of random codewords and codeword/bit error rate (CER/BER) curve computation. For this purpose, a system on chip (SoC) field-programmable gate array (FPGA) is used, implementing in the programmable hardware part several replicas of the decoder (exploiting the parallel capabilities of hardware) and managing the verification by parallel programming the software part of the SoC (exploiting the presence of multiple processing cores). The presented approach allows a seamless integration with high-level models, does not need expensive testing/emulation platforms and obtains the results in a reasonable amount of time.This work has been supported by Project TEC2017-86722-C4-3-R, funded by Spanish MICINN/AEI.Institute of Electrical and Electronics Engineers Inc.Universidad de Cantabria20212021-01-01journal articlehttp://purl.org/coar/resource_type/c_6501NAhttp://purl.org/coar/version/c_be7fb7dd8ff6fe43info:eu-repo/semantics/articlehttp://hdl.handle.net/10902/20523IEEE Communications Letters, 2021, 25(1), 127-131reponame:UCrea Repositorio Abierto de la Universidad de Cantabriainstname:Universidad de Cantabria (UC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:repositorio.unican.es:10902/205232026-06-02T12:39:31Z
dc.title.none.fl_str_mv Pre-silicon FEC decoding verification on SoC FPGAs
title Pre-silicon FEC decoding verification on SoC FPGAs
spellingShingle Pre-silicon FEC decoding verification on SoC FPGAs
Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X
Verification
Platform FPGAs
Prototyping
Emulation
BER/CER testing
title_short Pre-silicon FEC decoding verification on SoC FPGAs
title_full Pre-silicon FEC decoding verification on SoC FPGAs
title_fullStr Pre-silicon FEC decoding verification on SoC FPGAs
title_full_unstemmed Pre-silicon FEC decoding verification on SoC FPGAs
title_sort Pre-silicon FEC decoding verification on SoC FPGAs
dc.creator.none.fl_str_mv Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X
Abad García, Carlos
Álvarez Ruiz, Ángel
Ugarte Olano, Íñigo
Sánchez Espeso, Pablo Pedro
author Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X
author_facet Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X
Abad García, Carlos
Álvarez Ruiz, Ángel
Ugarte Olano, Íñigo
Sánchez Espeso, Pablo Pedro
author_role author
author2 Abad García, Carlos
Álvarez Ruiz, Ángel
Ugarte Olano, Íñigo
Sánchez Espeso, Pablo Pedro
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Universidad de Cantabria
dc.subject.none.fl_str_mv Verification
Platform FPGAs
Prototyping
Emulation
BER/CER testing
topic Verification
Platform FPGAs
Prototyping
Emulation
BER/CER testing
description Forward error correction (FEC) decoding hardware modules are challenging to verify at pre-silicon stage, when they are usually described at register-transfer (RT)/logic level with a hardware description language (HDL). They tend to hide faults due to their inherent tendency to correct errors and the required simulations with a massive insertion of inputs are too slow. In this work, two verification techniques based on FPGA-prototyping are applied in order to complement the mentioned simulations: golden model vs implementation matching with thousands of random codewords and codeword/bit error rate (CER/BER) curve computation. For this purpose, a system on chip (SoC) field-programmable gate array (FPGA) is used, implementing in the programmable hardware part several replicas of the decoder (exploiting the parallel capabilities of hardware) and managing the verification by parallel programming the software part of the SoC (exploiting the presence of multiple processing cores). The presented approach allows a seamless integration with high-level models, does not need expensive testing/emulation platforms and obtains the results in a reasonable amount of time.
publishDate 2021
dc.date.none.fl_str_mv 2021
2021-01-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
NA
http://purl.org/coar/version/c_be7fb7dd8ff6fe43
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/10902/20523
url http://hdl.handle.net/10902/20523
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers Inc.
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers Inc.
dc.source.none.fl_str_mv IEEE Communications Letters, 2021, 25(1), 127-131
reponame:UCrea Repositorio Abierto de la Universidad de Cantabria
instname:Universidad de Cantabria (UC)
instname_str Universidad de Cantabria (UC)
reponame_str UCrea Repositorio Abierto de la Universidad de Cantabria
collection UCrea Repositorio Abierto de la Universidad de Cantabria
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300719

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