A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI

Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-ze...

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Detalhes bibliográficos
Autores: Diaz-Fortuny, Javier|||0000-0002-8186-071X, Martin Martinez, Javier|||0000-0001-5938-5898, Rodríguez Martínez, Rosana|||0000-0002-4565-6703, Castro-Lopez, Rafael|||0000-0002-6247-3124, Roca, Elisenda|||0000-0001-6260-6495, Aragones, Xavier|||0000-0003-1352-8675, Barajas, Enrique|||0000-0002-2072-2268, Mateo, Diego|||0000-0001-5996-9092, Fernandez, Francisco V.|||0000-0001-8682-2280, Nafria, Montserrat|||0000-0002-9549-2890
Tipo de documento: artigo
Data de publicação:2019
País:España
Recursos:Universitat Autònoma de Barcelona
Repositório:Dipòsit Digital de Documents de la UAB
Idioma:inglês
OAI Identifier:oai:ddd.uab.cat:249157
Acesso em linha:https://ddd.uab.cat/record/249157
https://dx.doi.org/urn:doi:10.1109/JSSC.2018.2881923
Access Level:Acceso aberto
Palavra-chave:Aging
Bias temperature instability (BTI)
CMOS
Degradation
Hot carrier injection (HCI)
Negative BTI (NBTI)
Positive BTI (PBTI)
Random telegraph noise (RTN)
Reliability
Statistical characterization
Variability
Descrição
Resumo:Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 mu m(2).

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