Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new para...

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Detalles Bibliográficos
Autores: Cortadella, Jordi|||0000-0001-8114-250X, Kondratyev, Alex, Lavagno, Luciano, Sotiriou, Christos
Tipo de recurso: artículo
Fecha de publicación:2006
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/126455
Acceso en línea:https://hdl.handle.net/2117/126455
https://dx.doi.org/10.1109/TCAD.2005.860958
Access Level:acceso abierto
Palabra clave:Asynchronous circuits
Integrated circuits -- Design and construction
Logic design
Concurrent systems
Desynchronization
Electronic design automation
Handshake protocols
Synthesis
Circuits asíncrons
Circuits integrats -- Disseny i construcció
Estructura lògica
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
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spelling Desynchronization: Synthesis of asynchronous circuits from synchronous specificationsCortadella, Jordi|||0000-0001-8114-250XKondratyev, AlexLavagno, LucianoSotiriou, ChristosAsynchronous circuitsIntegrated circuits -- Design and constructionLogic designConcurrent systemsDesynchronizationElectronic design automationHandshake protocolsSynthesisCircuits asíncronsCircuits integrats -- Disseny i construccióEstructura lògicaÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integratsAsynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture.Peer Reviewed20062006-10-0120192019-01-10journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/126455https://dx.doi.org/10.1109/TCAD.2005.860958reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/1264552026-05-27T15:37:01Z
dc.title.none.fl_str_mv Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
title Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
spellingShingle Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
Cortadella, Jordi|||0000-0001-8114-250X
Asynchronous circuits
Integrated circuits -- Design and construction
Logic design
Concurrent systems
Desynchronization
Electronic design automation
Handshake protocols
Synthesis
Circuits asíncrons
Circuits integrats -- Disseny i construcció
Estructura lògica
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
title_short Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
title_full Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
title_fullStr Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
title_full_unstemmed Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
title_sort Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
dc.creator.none.fl_str_mv Cortadella, Jordi|||0000-0001-8114-250X
Kondratyev, Alex
Lavagno, Luciano
Sotiriou, Christos
author Cortadella, Jordi|||0000-0001-8114-250X
author_facet Cortadella, Jordi|||0000-0001-8114-250X
Kondratyev, Alex
Lavagno, Luciano
Sotiriou, Christos
author_role author
author2 Kondratyev, Alex
Lavagno, Luciano
Sotiriou, Christos
author2_role author
author
author
dc.subject.none.fl_str_mv Asynchronous circuits
Integrated circuits -- Design and construction
Logic design
Concurrent systems
Desynchronization
Electronic design automation
Handshake protocols
Synthesis
Circuits asíncrons
Circuits integrats -- Disseny i construcció
Estructura lògica
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
topic Asynchronous circuits
Integrated circuits -- Design and construction
Logic design
Concurrent systems
Desynchronization
Electronic design automation
Handshake protocols
Synthesis
Circuits asíncrons
Circuits integrats -- Disseny i construcció
Estructura lògica
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
description Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture.
publishDate 2006
dc.date.none.fl_str_mv 2006
2006-10-01
2019
2019-01-10
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/126455
https://dx.doi.org/10.1109/TCAD.2005.860958
url https://hdl.handle.net/2117/126455
https://dx.doi.org/10.1109/TCAD.2005.860958
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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