Fallos intermitentes: análisis de causas y efectos, nuevos modelos de fallos y técnicas de mitigación
[EN] From the first integrated circuit was developed to very large scale integration (VLSI) technology, the hardware of computer systems has had an immense evolution. Moore's Law, which predicts that the number of transistors that can be integrated on a chip doubles every year, has been acc...
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| Format: | doctoral thesis |
| Publication Date: | 2015 |
| Country: | España |
| Institution: | Universitat Politècnica de València (UPV) |
| Repository: | RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia |
| Language: | Spanish |
| OAI Identifier: | oai:riunet.upv.es:10251/59452 |
| Online Access: | https://riunet.upv.es/handle/10251/59452 |
| Access Level: | Open access |
| Keyword: | Fallos intermitentes Códigos correctores de errores Diseño digital Tecnología VLSI Confiabilidad Tolerancia a fallos Inyección de fallos Modelado y simulación ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES |
| Summary: | [EN] From the first integrated circuit was developed to very large scale integration (VLSI) technology, the hardware of computer systems has had an immense evolution. Moore's Law, which predicts that the number of transistors that can be integrated on a chip doubles every year, has been accomplished for decades thanks to the aggressive reduction of transistors size. This has allowed increasing its frequency, achieving higher performance with lower consumption, but at the expense of a reliability penalty. The number of defects are raising due to variations in the increasingly complex manufacturing process. Intermittent faults, one of the fundamental issues affecting the reliability of current and future digital VLSI circuits technologies, are studied in this thesis. In the past, intermittent faults have been considered the prelude to permanent faults. Nowadays, the occurrence of intermittent faults caused by variations in the manufacturing process not affecting permanently has increased. Errors induced by intermittent and transient faults manifest similarly, although intermittent faults are usually grouped in bursts and they are activated repeatedly and non-deterministically in the same place. In addition, intermittent faults can be activated and deactivated by changes in temperature, voltage and frequency. In this thesis, the effects of intermittent faults in digital systems have been analyzed by using simulation-based fault injection. This methodology allows introducing faults in a controlled manner. After an extensive literature review to understand the physical mechanisms of intermittent faults, new intermittent fault models at gate and register transfer levels have been proposed. These new fault models have been used to analyze the effects of intermittent faults in different microprocessors models, as well as the influence of several parameters. To mitigate these effects, various fault tolerance techniques have been studied in this thesis, in order to determine whether they are suitable to tolerate intermittent faults. Results show that the error detection mechanisms work properly, but the error recovery mechanisms need to be improved. Error correction codes (ECC) is a well-known fault tolerance technique. This thesis proposes a new family of ECCs specially designed to tolerate faults when the fault rate is not equal in all bits in a word, such as in the presence of intermittent faults. As these faults may also present a fault rate variable along time, a fault tolerance mechanism whose behavior adapts to the temporal evolution of error conditions can use the new ECCs proposed. |
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