Conversor DSB-SSB a capacitores chaveados por transformador de Hilbert em tecnologia CMOS de 180 nm
The realization of an analog integrated circuit for conversion of Double-Sideband (DSB) amplitude-modulated signals into Single-Sideband (SSB) is presented. Implemented by discrete-time switched-capacitor circuits, it adopts an Infinite Impulse Response (IIR) filter to realize a Hilbert transformer...
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| Tipo de recurso: | tesis doctoral |
| Estado: | Versión publicada |
| Fecha de publicación: | 2017 |
| País: | Brasil |
| Institución: | Universidade Federal do Rio de Janeiro (UFRJ) |
| Repositorio: | Repositório Institucional da UFRJ |
| Idioma: | portugués |
| OAI Identifier: | oai:pantheon.ufrj.br:11422/6234 |
| Acceso en línea: | http://hdl.handle.net/11422/6234 |
| Access Level: | acceso abierto |
| Palabra clave: | Circuitos integrados MOS Transformadores e Reatores Circuito com capacitores chaveados CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA::CIRCUITOS ELETRICOS, MAGNETICOS E ELETRONICOS::CIRCUITOS ELETRONICOS |
| Sumario: | The realization of an analog integrated circuit for conversion of Double-Sideband (DSB) amplitude-modulated signals into Single-Sideband (SSB) is presented. Implemented by discrete-time switched-capacitor circuits, it adopts an Infinite Impulse Response (IIR) filter to realize a Hilbert transformer as alternative to digital implementations which take advantage of high processing capacity from parallel digital circuits to obtain the Hilbert transformer by means of high-order Finite Impulse Response (FIR) filters. Fabricated in a 180 nm CMOS technology with metal-metal (MiM) capacitors, the use of structurally all-pass filters greatly reduces the converter’s sensitivity to capacitor mismatch. For 1.8 V power supply and 1 V differential input/output signals, experimental results show the converter achieves Image Rejection Ratio (IRR) greater than 39.5 dB for Lower-Sideband (LSB) modulation and 38.0 dB for Upper-Sideband (USB) modulation for input signals ranging from 25% to 75% of the carrier frequency. These figures are higher than previous analog circuit proposals and comparable to digital implementations of state-of-the-art integrated circuits. Its silicon area is 1.09 mm2 and the converter consumes only 17.7 mW for 1 MHz sampling frequency while its IRR presents standard deviation of only 0.5 dB among 20 chip samples. |
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