Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects

CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology...

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Authors: Copetti, Thiago Santos, Balen, Tiago Roberto, Brum, Eduardo Longo de, Aquistapace, Caroline Oliveira, Poehls, Leticia Maria Bolzani
Format: article
Status:Published version
Publication Date:2020
Country:Brasil
Institution:Universidade Federal do Rio Grande do Sul (UFRGS)
Repository:Repositório Institucional da UFRGS
Language:English
OAI Identifier:oai:www.lume.ufrgs.br:10183/223170
Online Access:http://hdl.handle.net/10183/223170
Access Level:Open access
Keyword:Dispositivos eletrônicos
Detecção de falhas
Transistores
CMOS
FinFET
SRAMs
Resistive defects
Power supply voltage
Test
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spelling 2021-07-06T04:45:16Z20201573-0727http://hdl.handle.net/10183/223170001127203CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology.application/pdfengJournal of electronic testing : theory and applications. Dordrecht : Kluwer. Vol. 36 (2020), p. 271-284Dispositivos eletrônicosDetecção de falhasTransistoresCMOSFinFETSRAMsResistive defectsPower supply voltageTestComparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defectsEstrangeiroinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSCopetti, Thiago SantosBalen, Tiago RobertoBrum, Eduardo Longo deAquistapace, Caroline OliveiraPoehls, Leticia Maria BolzaniTEXT001127203.pdf.txt001127203.pdf.txtExtracted Texttext/plain62983http://www.lume.ufrgs.br/bitstream/10183/223170/2/001127203.pdf.txtb4da38634c5f6d8ff044efff2f9ecb1dMD52ORIGINAL001127203.pdfTexto completo (inglês)application/pdf887355http://www.lume.ufrgs.br/bitstream/10183/223170/1/001127203.pdfa03d8c54c6471bd79d831248d262bbe4MD5110183/2231702021-08-04 04:36:04.894041oai:www.lume.ufrgs.br:10183/223170Repositório InstitucionalPUBhttps://lume.ufrgs.br/oai/requestlume@ufrgs.bropendoar:2021-08-04T07:36:04Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false
dc.title.pt_BR.fl_str_mv Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects
title Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects
spellingShingle Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects
Copetti, Thiago Santos
Dispositivos eletrônicos
Detecção de falhas
Transistores
CMOS
FinFET
SRAMs
Resistive defects
Power supply voltage
Test
title_short Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects
title_full Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects
title_fullStr Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects
title_full_unstemmed Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects
title_sort Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects
dc.creator.none.fl_str_mv Copetti, Thiago Santos
Balen, Tiago Roberto
Brum, Eduardo Longo de
Aquistapace, Caroline Oliveira
Poehls, Leticia Maria Bolzani
author Copetti, Thiago Santos
author_facet Copetti, Thiago Santos
Balen, Tiago Roberto
Brum, Eduardo Longo de
Aquistapace, Caroline Oliveira
Poehls, Leticia Maria Bolzani
author_role author
author2 Balen, Tiago Roberto
Brum, Eduardo Longo de
Aquistapace, Caroline Oliveira
Poehls, Leticia Maria Bolzani
author2_role author
author
author
author
dc.subject.por.fl_str_mv Dispositivos eletrônicos
Detecção de falhas
Transistores
topic Dispositivos eletrônicos
Detecção de falhas
Transistores
CMOS
FinFET
SRAMs
Resistive defects
Power supply voltage
Test
dc.subject.eng.fl_str_mv CMOS
FinFET
SRAMs
Resistive defects
Power supply voltage
Test
description CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology.
publishDate 2020
dc.date.issued.fl_str_mv 2020
dc.date.accessioned.fl_str_mv 2021-07-06T04:45:16Z
dc.type.driver.fl_str_mv Estrangeiro
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dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
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dc.identifier.uri.fl_str_mv http://hdl.handle.net/10183/223170
dc.identifier.issn.pt_BR.fl_str_mv 1573-0727
dc.identifier.nrb.pt_BR.fl_str_mv 001127203
identifier_str_mv 1573-0727
001127203
url http://hdl.handle.net/10183/223170
dc.language.iso.fl_str_mv eng
language eng
dc.relation.ispartof.pt_BR.fl_str_mv Journal of electronic testing : theory and applications. Dordrecht : Kluwer. Vol. 36 (2020), p. 271-284
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:Repositório Institucional da UFRGS
instname:Universidade Federal do Rio Grande do Sul (UFRGS)
instacron:UFRGS
instname_str Universidade Federal do Rio Grande do Sul (UFRGS)
instacron_str UFRGS
institution UFRGS
reponame_str Repositório Institucional da UFRGS
collection Repositório Institucional da UFRGS
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