A Verilog HDL digital architecture for delay calculation

A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of...

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Autores: Chacón-Rodríguez, A., Martín-Pirchio, F. N., Julian, Pedro Marcelo, Mandolesi, Pablo Sergio
Formato: artículo
Estado:Versión publicada
Fecha de publicación:2007
País:Argentina
Recursos:Consejo Nacional de Investigaciones Científicas y Técnicas
Repositorio:CONICET Digital (CONICET)
Idioma:inglés
OAI Identifier:oai:ri.conicet.gov.ar:11336/105848
Acesso em linha:http://hdl.handle.net/11336/105848
Access Level:acceso abierto
Palavra-chave:VERILOG
FPGA
LOW POWER
DIGITAL CMOS VLSI
https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
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spelling A Verilog HDL digital architecture for delay calculationChacón-Rodríguez, A.Martín-Pirchio, F. N.Julian, Pedro MarceloMandolesi, Pablo SergioVERILOGFPGALOW POWERDIGITAL CMOS VLSIhttps://purl.org/becyt/ford/2.2https://purl.org/becyt/ford/2A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations.Fil: Chacón-Rodríguez, A.. Universidad de Mar del Plata. Laboratorio de Componentes Electrónicos; ArgentinaFil: Martín-Pirchio, F. N.. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; ArgentinaFil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Mandolesi, Pablo Sergio. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; ArgentinaPlanta Piloto de Ingeniería Química2007-02info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/105848Chacón-Rodríguez, A.; Martín-Pirchio, F. N.; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; A Verilog HDL digital architecture for delay calculation; Planta Piloto de Ingeniería Química; Latin American Applied Research; 37; 1; 2-2007; 41-450327-07931851-8796CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/url/http://www.laar.plapiqui.edu.ar/OJS/public/site/volumens/indexes/i37_01.htminfo:eu-repo/semantics/altIdentifier/url/http://www.laar.plapiqui.edu.ar/OJS/public/site/volumens/indexes/artic_v3701/vol_37_1_pag41.pdfinfo:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-sa/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2024-05-08T13:45:42Zoai:ri.conicet.gov.ar:11336/105848instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982024-05-08 13:45:42.896CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv A Verilog HDL digital architecture for delay calculation
title A Verilog HDL digital architecture for delay calculation
spellingShingle A Verilog HDL digital architecture for delay calculation
Chacón-Rodríguez, A.
VERILOG
FPGA
LOW POWER
DIGITAL CMOS VLSI
https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
title_short A Verilog HDL digital architecture for delay calculation
title_full A Verilog HDL digital architecture for delay calculation
title_fullStr A Verilog HDL digital architecture for delay calculation
title_full_unstemmed A Verilog HDL digital architecture for delay calculation
title_sort A Verilog HDL digital architecture for delay calculation
dc.creator.none.fl_str_mv Chacón-Rodríguez, A.
Martín-Pirchio, F. N.
Julian, Pedro Marcelo
Mandolesi, Pablo Sergio
author Chacón-Rodríguez, A.
author_facet Chacón-Rodríguez, A.
Martín-Pirchio, F. N.
Julian, Pedro Marcelo
Mandolesi, Pablo Sergio
author_role author
author2 Martín-Pirchio, F. N.
Julian, Pedro Marcelo
Mandolesi, Pablo Sergio
author2_role author
author
author
dc.subject.none.fl_str_mv VERILOG
FPGA
LOW POWER
DIGITAL CMOS VLSI
https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
topic VERILOG
FPGA
LOW POWER
DIGITAL CMOS VLSI
https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
description A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations.
publishDate 2007
dc.date.none.fl_str_mv 2007-02
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/105848
Chacón-Rodríguez, A.; Martín-Pirchio, F. N.; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; A Verilog HDL digital architecture for delay calculation; Planta Piloto de Ingeniería Química; Latin American Applied Research; 37; 1; 2-2007; 41-45
0327-0793
1851-8796
CONICET Digital
CONICET
url http://hdl.handle.net/11336/105848
identifier_str_mv Chacón-Rodríguez, A.; Martín-Pirchio, F. N.; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; A Verilog HDL digital architecture for delay calculation; Planta Piloto de Ingeniería Química; Latin American Applied Research; 37; 1; 2-2007; 41-45
0327-0793
1851-8796
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/http://www.laar.plapiqui.edu.ar/OJS/public/site/volumens/indexes/i37_01.htm
info:eu-repo/semantics/altIdentifier/url/http://www.laar.plapiqui.edu.ar/OJS/public/site/volumens/indexes/artic_v3701/vol_37_1_pag41.pdf
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
application/pdf
dc.publisher.none.fl_str_mv Planta Piloto de Ingeniería Química
publisher.none.fl_str_mv Planta Piloto de Ingeniería Química
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
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score 15.811543

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