Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises a linear array of 48 × 48 processing ele...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2018 |
| País: | Argentina |
| Institución: | Consejo Nacional de Investigaciones Científicas y Técnicas |
| Repositorio: | CONICET Digital (CONICET) |
| Idioma: | inglés |
| OAI Identifier: | oai:ri.conicet.gov.ar:11336/86483 |
| Acceso en línea: | http://hdl.handle.net/11336/86483 |
| Access Level: | acceso abierto |
| Palabra clave: | VLSI Internet of Things Neural chips https://purl.org/becyt/ford/2.2 https://purl.org/becyt/ford/2 |
| Sumario: | This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight-neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low-voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V. |
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