Minimization of the line resistance impact on memdiode-based simulations of multilayer perceptron arrays applied to pattern recognition
In this paper, we extend the application of the Quasi-Static Memdiode model to the real-istic SPICE simulation of memristor-based single (SLPs) and multilayer perceptrons (MLPs) in-tended for large dataset pattern recognition. By considering ex-situ training and the classification of the hand-writte...
| Autores: | , , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2021 |
| País: | Argentina |
| Institución: | Consejo Nacional de Investigaciones Científicas y Técnicas |
| Repositorio: | CONICET Digital (CONICET) |
| Idioma: | inglés |
| OAI Identifier: | oai:ri.conicet.gov.ar:11336/165149 |
| Acceso en línea: | http://hdl.handle.net/11336/165149 |
| Access Level: | acceso abierto |
| Palabra clave: | CROSS-POINT MEMORY MEMRISTOR MULTILAYER PERCEPTRON NEUROMORPHIC PATTERN RECOGNITION RESISTIVE-SWITCHING RRAM https://purl.org/becyt/ford/1.3 https://purl.org/becyt/ford/1 |
| Sumario: | In this paper, we extend the application of the Quasi-Static Memdiode model to the real-istic SPICE simulation of memristor-based single (SLPs) and multilayer perceptrons (MLPs) in-tended for large dataset pattern recognition. By considering ex-situ training and the classification of the hand-written characters of the MNIST database, we evaluate the degradation of the inference accuracy due to the interconnection resistances for MLPs involving up to three hidden neural layers. Two approaches to reduce the impact of the line resistance are considered and implemented in our simulations, they are the inclusion of an iterative calibration algorithm and the partitioning of the synaptic layers into smaller blocks. The obtained results indicate that MLPs are more sensitive to the line resistance effect than SLPs and that partitioning is the most effective way to minimize the impact of high line resistance values. |
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