Utilizing block size variability to enhance instruction fetch rate
In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program...
| Autores: | , |
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| Tipo de documento: | artigo |
| Estado: | Versão publicada |
| Data de publicação: | 2007 |
| País: | Argentina |
| Recursos: | Universidad Nacional de La Plata |
| Repositório: | SEDICI (UNLP) |
| Idioma: | inglês |
| OAI Identifier: | oai:sedici.unlp.edu.ar:10915/9548 |
| Acesso em linha: | http://sedici.unlp.edu.ar/handle/10915/9548 |
| Access Level: | Acceso aberto |
| Palavra-chave: | Ciencias Informáticas Cache memories Variable-Sized Block Cache (VSBC) |
| Resumo: | In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program. Current trace-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. Our cache also allows storage of basic blocks of arbitrary sizes, in multiple-way cache structure. An overall comparison of trace miss rate and average trace length shows VSBC to be a better performing cache scheme than TC, using SPECint2000 integer benchmarks. |
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