A system on a programmable chip architecture for data-dependent superimposed training channel estimation

Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of the filters that remove the distortion of the data. Nevertheless, a part of the available bandwidth has...

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Detalles Bibliográficos
Autores: FERNANDO MARTIN DEL CAMPO RAMIREZ, RENE ARMANDO CUMPLIDO PARRA, JOSE ROBERTO PEREZ ANDRADE, ALDO GUSTAVO OROZCO LUGO
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2009
País:México
Institución:Instituto Nacional de Astrofísica, Óptica y Electrónica
Repositorio:Repositorio Institucional del INAOE
Idioma:inglés
OAI Identifier:oai:inaoe.repositorioinstitucional.mx:1009/1171
Acceso en línea:http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1171
Access Level:acceso abierto
Palabra clave:info:eu-repo/classification/cti/1
info:eu-repo/classification/cti/12
info:eu-repo/classification/cti/1203
Descripción
Sumario:Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of the filters that remove the distortion of the data. Nevertheless, a part of the available bandwidth has to be destined to these symbols. Until now, no alternative solution has demonstrated to be fully satisfying for commercial use, but one technique that looks promising is superimposed training (ST). This work describes a hybrid software-hardware FPGA implementation of a recent algorithm that belongs to the ST family, known as Datadependent Superimposed Training (DDST), which does not need extra bandwidth for its training sequences (TS) as it adds them arithmetically to the data. DDST also adds a third sequence known as data-dependent sequence, that destroys the interference caused by the data over the TS. As DDST’s computational burden is too high for the commercial processors used in mobile systems, a System on a Programmable Chip (SOPC) approach is used in order to solve the problem.