A Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validation
The optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test...
| Autores: | , , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2016 |
| País: | México |
| Institución: | Instituto Tecnológico y de Estudios Superiores de Occidente |
| Repositorio: | Repositorio Institucional del ITESO |
| Idioma: | inglés |
| OAI Identifier: | oai:rei.iteso.mx:11117/6003 |
| Acceso en línea: | http://hdl.handle.net/11117/6003 |
| Access Level: | acceso abierto |
| Palabra clave: | Post-silicon Validation Jitter System Margining Eye Diagram |
| Sumario: | The optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose an innovative objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-Si validation time. |
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