A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique

This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated usin...

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Detalles Bibliográficos
Autores: J.J. Ocampo-Hidalgo, I. Vázquez-Álvarez, S. Sandoval-Perez, R. Z. García-Lozano, M. A. Gurrola, J. E. Molinar-Solis
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2017
País:México
Institución:Universidad de Guadalajara
Repositorio:Redalyc-UDG
OAI Identifier:oai:redalyc.org:64352303011
Acceso en línea:https://www.redalyc.org/articulo.oa?id=64352303011
Access Level:acceso abierto
Palabra clave:Ingeniería
quasi
micro
power
low voltage
floating gate circuits
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spelling A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate techniqueJ.J. Ocampo-HidalgoI. Vázquez-ÁlvarezS. Sandoval-PerezR. Z. García-LozanoM. A. GurrolaJ. E. Molinar-SolisIngenieríaquasimicropowerlow voltagefloating gate circuitsThis paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain-bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.Universidad Nacional de Colombia2017info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdf0120-5609https://www.redalyc.org/articulo.oa?id=64352303011Ingeniería e Investigación (Colombia) Num.2 Vol.37reponame:Redalyc-UDGinstname:Universidad de Guadalajarainstacron:UDGenhttp://www.redalyc.org/revista.oa?id=643Ingeniería e Investigacióninfo:eu-repo/semantics/openAccessoai:redalyc.org:643523030112026-01-29T04:44:49Z
dc.title.none.fl_str_mv A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
title A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
spellingShingle A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
J.J. Ocampo-Hidalgo
Ingeniería
quasi
micro
power
low voltage
floating gate circuits
title_short A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
title_full A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
title_fullStr A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
title_full_unstemmed A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
title_sort A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
dc.creator.none.fl_str_mv J.J. Ocampo-Hidalgo
I. Vázquez-Álvarez
S. Sandoval-Perez
R. Z. García-Lozano
M. A. Gurrola
J. E. Molinar-Solis
author J.J. Ocampo-Hidalgo
author_facet J.J. Ocampo-Hidalgo
I. Vázquez-Álvarez
S. Sandoval-Perez
R. Z. García-Lozano
M. A. Gurrola
J. E. Molinar-Solis
author_role author
author2 I. Vázquez-Álvarez
S. Sandoval-Perez
R. Z. García-Lozano
M. A. Gurrola
J. E. Molinar-Solis
author2_role author
author
author
author
author
dc.subject.none.fl_str_mv Ingeniería
quasi
micro
power
low voltage
floating gate circuits
topic Ingeniería
quasi
micro
power
low voltage
floating gate circuits
description This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain-bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.
publishDate 2017
dc.date.none.fl_str_mv 2017
dc.type.none.fl_str_mv info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv 0120-5609
https://www.redalyc.org/articulo.oa?id=64352303011
identifier_str_mv 0120-5609
url https://www.redalyc.org/articulo.oa?id=64352303011
dc.language.none.fl_str_mv en
language_invalid_str_mv en
dc.relation.none.fl_str_mv http://www.redalyc.org/revista.oa?id=643
dc.rights.none.fl_str_mv Ingeniería e Investigación
info:eu-repo/semantics/openAccess
rights_invalid_str_mv Ingeniería e Investigación
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universidad Nacional de Colombia
publisher.none.fl_str_mv Universidad Nacional de Colombia
dc.source.none.fl_str_mv Ingeniería e Investigación (Colombia) Num.2 Vol.37
reponame:Redalyc-UDG
instname:Universidad de Guadalajara
instacron:UDG
instname_str Universidad de Guadalajara
instacron_str UDG
institution UDG
reponame_str Redalyc-UDG
collection Redalyc-UDG
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 14.964252

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