Arquitectura basada en FPGA para la recuperación estereo en tiempo real para una cámara inteligente
Stereo vision allows to calculate a tridimentional structure of a scene from two or more captured images taken from diferents points of view. The basic idea of stereo algorithms is to find the point of one scene captured with a image sensor with its respective point projected in another image sensor...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2008 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | español |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/437 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/437 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Arrays de puertas programables en campo/Field programmable gate arrays info:eu-repo/classification/Procesamiento de imágenes estéreo/Stereo image processing info:eu-repo/classification/Visión/Vision info:eu-repo/classification/cti/7 info:eu-repo/classification/cti/33 info:eu-repo/classification/cti/3307 |
| Sumario: | Stereo vision allows to calculate a tridimentional structure of a scene from two or more captured images taken from diferents points of view. The basic idea of stereo algorithms is to find the point of one scene captured with a image sensor with its respective point projected in another image sensor.The search proccesing requieres a high number of operations. A real time application is limited by the execution of those operations and the data access. In this work is proposed a real-time 3D recovery stereo vision system, embebed on a FPGA. The integration of a FPGA based hardware arquitecture with a pair of stereo images sensors results into a 3D smart camera. The hardware arquitecture design was based on an independienttime data analisys. The performance results shows that the propose arquitecture can process 30 frame per second with 640x480 pixels images. The implementation results shows that a 60% FPGA resource were used (6,580 flip-flops). The hardware arquitecture comparative is not easy to stablish, however, we can use the processed pixels per second number as a comparation metric. Using this metric, it can be stablished that the arquitecture in this work has a better performance than the found in the literature. One of the hardware arquitecture contribution is the variable performance configuration based on images sizes, search window size and disparity range size. Any configuration achieves a real time performance, but the FPGA usage increases. |
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