Metodología para la polarización de amplificadores retroalimentados
The design of a proper bias scheme for analog circuits constitutes a problem which requires design experience and encyclopedic knowledge of circuit topologies. Although there are many design rules which may be used to bias some analog circuits, a systematic procedure is still lacking to carry out th...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2009 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | español |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/382 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/382 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Teoría de grafos/Graph theory info:eu-repo/classification/Amplificadores/Amplifiers info:eu-repo/classification/Polarización/Polarisation info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
| Sumario: | The design of a proper bias scheme for analog circuits constitutes a problem which requires design experience and encyclopedic knowledge of circuit topologies. Although there are many design rules which may be used to bias some analog circuits, a systematic procedure is still lacking to carry out this task. This thesis presents a proposal for the biasing of circuits using a methodology based on graph theory which covers the aspects related to their small-signal behavior as well as its DC response. The methodology is focused on the biasing of nullor-based negative feedback amplifiers. The new methodology is capable of generating a suitable biasing scheme for negative feedback amplifiers with active elements such as bipolar and MOS transistors for the nullor implementation. The proposed methodology is based on manipulations of the graph associated to the circuit to be biased, separating and grouping elements in subgraphs according to the task that they perform on the circuit. Special care is dedicated to the DC filtering network, which, albeit simple in concept, turns out to be of great help in the separation of AC and DC signals. This application becomes more obvious at graph level when it comes to keep the meshes of DC components free from AC elements. Several examples are shown to illustrate the use of the methodology. |
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