Hardware and Software Co-design: An Architecture Proposal for a Network-on-Chip Switch based on Bufferless Data Flow
The use of on chip networks as interconnection media fo r systems implemented in FPGA s is limited by the amount of logical resources necessary to deploy the network in the target device, and the time necessary to adjust the network parameters to achieve the perfo rmance goal for the system. In this...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2014 |
| País: | México |
| Institución: | Universidad de Guadalajara |
| Repositorio: | Redalyc-UDG |
| OAI Identifier: | oai:redalyc.org:47429971015 |
| Acceso en línea: | https://www.redalyc.org/articulo.oa?id=47429971015 |
| Access Level: | acceso abierto |
| Palabra clave: | Ingeniería NoC SoC RTL |
| Sumario: | The use of on chip networks as interconnection media fo r systems implemented in FPGA s is limited by the amount of logical resources necessary to deploy the network in the target device, and the time necessary to adjust the network parameters to achieve the perfo rmance goal for the system. In this paper we present a switch architecture, with data flow control based on circuit switching and aim ed for on-chip networks with a Spidergon topology, which seeks to reduce the area occupied without severely affect ing the overall network perf ormance. As a result, we obtained a switch that requires only 114 slices in its most economic version on a Virtex 4- device. We also provide a performance profile, obtained by subjecting a network form ed by these switches to di fferent synthetic workloads within a simulator. This simulator was developed as part of the design flow of the swit ch, and it proves to be an essential tool for the test and validation process. |
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