Compact low-power calibration mini-DACs for neural arrays with programmable weights

This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumpt...

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Detalles Bibliográficos
Autores: Linares Barranco, Bernabé, Serrano Gotarredona, María Teresa, Serrano Gotarredona, Rafael
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2003
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/76270
Acceso en línea:https://hdl.handle.net/11441/76270
https://doi.org/10.1109/TNN.2003.816370
Access Level:acceso abierto
Palabra clave:Analog design
Calibration
Current splitters
Digital-to-analog converters
Fuzzy circuits
Neural networks
Subthreshold
Weak inversion
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spelling Compact low-power calibration mini-DACs for neural arrays with programmable weightsLinares Barranco, BernabéSerrano Gotarredona, María TeresaSerrano Gotarredona, RafaelAnalog designCalibrationCurrent splittersDigital-to-analog convertersFuzzy circuitsNeural networksSubthresholdWeak inversionThis paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47% (1.1 bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by a factor of 10 (4.8% or 4.4 bits), which makes these DACs viable for low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated through examples, to obtain calibrated mini-DACs of a given target precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons.Gobierno de España TIC1999-0446-C02-02, TIC2000-0406-P4-05, FIT-07000/2002/921, TIC2002-10878-EEuropean Union IST- 2001-34124Institute of Electrical and Electronics EngineersArquitectura y Tecnología de ComputadoresGobierno de EspañaEuropean Union (UE)2003info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/76270https://doi.org/10.1109/TNN.2003.816370reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIEEE Transactions on Neural Networks, 14 (5), 1207-1216.TIC1999-0446-C02-02TIC2000-0406-P4-05FIT-07000/2002/921TIC2002-10878-EIST- 2001-34124http://dx.doi.org/10.1109/TNN.2003.816370info:eu-repo/semantics/openAccessoai:idus.us.es:11441/762702026-06-17T12:51:07Z
dc.title.none.fl_str_mv Compact low-power calibration mini-DACs for neural arrays with programmable weights
title Compact low-power calibration mini-DACs for neural arrays with programmable weights
spellingShingle Compact low-power calibration mini-DACs for neural arrays with programmable weights
Linares Barranco, Bernabé
Analog design
Calibration
Current splitters
Digital-to-analog converters
Fuzzy circuits
Neural networks
Subthreshold
Weak inversion
title_short Compact low-power calibration mini-DACs for neural arrays with programmable weights
title_full Compact low-power calibration mini-DACs for neural arrays with programmable weights
title_fullStr Compact low-power calibration mini-DACs for neural arrays with programmable weights
title_full_unstemmed Compact low-power calibration mini-DACs for neural arrays with programmable weights
title_sort Compact low-power calibration mini-DACs for neural arrays with programmable weights
dc.creator.none.fl_str_mv Linares Barranco, Bernabé
Serrano Gotarredona, María Teresa
Serrano Gotarredona, Rafael
author Linares Barranco, Bernabé
author_facet Linares Barranco, Bernabé
Serrano Gotarredona, María Teresa
Serrano Gotarredona, Rafael
author_role author
author2 Serrano Gotarredona, María Teresa
Serrano Gotarredona, Rafael
author2_role author
author
dc.contributor.none.fl_str_mv Arquitectura y Tecnología de Computadores
Gobierno de España
European Union (UE)
dc.subject.none.fl_str_mv Analog design
Calibration
Current splitters
Digital-to-analog converters
Fuzzy circuits
Neural networks
Subthreshold
Weak inversion
topic Analog design
Calibration
Current splitters
Digital-to-analog converters
Fuzzy circuits
Neural networks
Subthreshold
Weak inversion
description This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47% (1.1 bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by a factor of 10 (4.8% or 4.4 bits), which makes these DACs viable for low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated through examples, to obtain calibrated mini-DACs of a given target precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons.
publishDate 2003
dc.date.none.fl_str_mv 2003
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/76270
https://doi.org/10.1109/TNN.2003.816370
url https://hdl.handle.net/11441/76270
https://doi.org/10.1109/TNN.2003.816370
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv IEEE Transactions on Neural Networks, 14 (5), 1207-1216.
TIC1999-0446-C02-02
TIC2000-0406-P4-05
FIT-07000/2002/921
TIC2002-10878-E
IST- 2001-34124
http://dx.doi.org/10.1109/TNN.2003.816370
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300719

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