Design and implementation of a PLL in a 65nm CMOS technology for X-Ray image sensors
This thesis presents the design and schematic-level validation of a Type-2, third-order Phase-Locked Loop (PLL) in 65nm CMOS technology, developed to address the data processing bottleneck for X-ray image sensors for industrial food inspection. The integer-N PLL is designed to generate a stable 3,2G...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/452700 |
| Acceso en línea: | https://hdl.handle.net/2117/452700 |
| Access Level: | acceso abierto |
| Palabra clave: | Metal oxide semiconductors, Complementary Frequency synthesizers Phase-locked loops PLL CMOS PFD CP VCO LPF DIV Metall-òxid-semiconductors complementaris Sintetitzadors de freqüència Llaços de seguiment de fase Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
| Sumario: | This thesis presents the design and schematic-level validation of a Type-2, third-order Phase-Locked Loop (PLL) in 65nm CMOS technology, developed to address the data processing bottleneck for X-ray image sensors for industrial food inspection. The integer-N PLL is designed to generate a stable 3,2GHz from a 100MHz reference, enabling faster, more accurate contaminant detection. Simulation results confirm the PLL achieves lock in approximately 13,8μs with a maximum RMS period jitter of 3,55ps. A critical analysis of the stand-alone ring VCO reveals high intrinsic phase noise (-70,2d dBc/Hz @ 1MHz), a key limitation of the current design. The work successfully demonstrates a functional frequency synthesizer, providing a robust foundation for future physical implementation and optimization. |
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