A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology
This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, or 4-bit internal resolution. The modulator is implemented with fully-differentia...
| Autores: | , , , , |
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| Formato: | artículo |
| Fecha de publicación: | 2000 |
| País: | España |
| Recursos: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositorio: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/3841 |
| Acesso em linha: | http://hdl.handle.net/10261/3841 |
| Access Level: | acceso abierto |
| Palavra-chave: | Analog-to-digital converters Sigma-Delta Modulators |
| Resumo: | This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, or 4-bit internal resolution. The modulator is implemented with fully-differential switched capacitor circuits in a CMOS 0.35-um digital technology. The estimated power consumption is 78mW, from a 3.3-V supply. |
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