Architecture and performance of the KM3NeT front-end firmware

[EN] The KM3NeT infrastructure consists of two deep-sea neutrino telescopes being deployed in the Mediterranean Sea. The telescopes will detect extraterrestrial and atmospheric neutrinos by means of the incident photons induced by the passage of relativistic charged particles through the seawater as...

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Detalles Bibliográficos
Autores: Aiello, Sebastiano, Albert, Arnauld, Alves Garre, Sergio, Aly, Zine, Ameli, Fabrizio, Andre, Michel, Androulakis, Giorgos, Anghinolfi, Marco, Anguita, Mancia, Anton, Gisela, Aublin, Julien, Bagatelas, Christos, Barbarino, Giancarlo, Baret, Bruny, Diego-Tortosa, Dídac, Martínez Mora, Juan Antonio, Poirè, Chiara, Ardid, Miguel|||0000-0002-3199-594X, Espinosa Roselló, Víctor|||0000-0001-8882-866X
Tipo de recurso: artículo
Fecha de publicación:2021
País:España
Institución:Universitat Politècnica de València (UPV)
Repositorio:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
Idioma:inglés
OAI Identifier:oai:riunet.upv.es:10251/187688
Acceso en línea:https://riunet.upv.es/handle/10251/187688
Access Level:acceso abierto
Palabra clave:Neutrino telescope
Acquisition firmware
Time to digital converters
KM3NeT
FISICA APLICADA
Descripción
Sumario:[EN] The KM3NeT infrastructure consists of two deep-sea neutrino telescopes being deployed in the Mediterranean Sea. The telescopes will detect extraterrestrial and atmospheric neutrinos by means of the incident photons induced by the passage of relativistic charged particles through the seawater as a consequence of a neutrino interaction. The telescopes are configured in a three-dimensional grid of digital optical modules, each hosting 31 photomultipliers. The photomultiplier signals produced by the incident Cherenkov photons are converted into digital information consisting of the integrated pulse duration and the time at which it surpasses a chosen threshold. The digitization is done by means of time to digital converters (TDCs) embedded in the field programmable gate array of the central logic board. Subsequently, a state machine formats the acquired data for its transmission to shore. We present the architecture and performance of the front-end firmware consisting of the TDCs and the state machine