Improving memory-centric architectures for accelerating cognitive computing workloads
(English) The rapid advancements in deep neural networks (DNNs) have led to increasingly complex and memory-intensive workloads, posing significant challenges for traditional computing architectures. Excessive data movement, computational inefficiencies, and energy constraints limit the scalability...
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| Tipo de recurso: | tesis doctoral |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/450564 |
| Acceso en línea: | https://hdl.handle.net/2117/450564 https://dx.doi.org/10.5821/dissertation-2117-450564 |
| Access Level: | acceso abierto |
| Palabra clave: | Memory-centric architectures AI acceleration and Data movement reduction 004 - Informàtica Àrees temàtiques de la UPC::Informàtica |
| Sumario: | (English) The rapid advancements in deep neural networks (DNNs) have led to increasingly complex and memory-intensive workloads, posing significant challenges for traditional computing architectures. Excessive data movement, computational inefficiencies, and energy constraints limit the scalability of DNN accelerators. This thesis addresses these challenges by proposing memory-centric approaches to optimize DNN execution through efficient quantization, in-memory processing, and data movement reduction. We first introduce DNA-TEQ, an adaptive exponential quantization scheme that minimizes memory footprint and eliminates the need for conventional multipliers, significantly enhancing energy efficiency. Experimental results show that DNA-TEQ reduces the memory footprint by 40% on average compared to the 8-bit integer baseline. The hardware processing-near-memory (PnM) accelerator designed to benefit from DNA-TEQ further improves inference latency by 1.5× while maintaining accuracy comparable to full-precision models. Next, we present QeiHaN, a PnM accelerator that employs base-2 exponential quantization and an implicit bit-shifting technique to reduce redundant memory accesses and optimize DNN inference. Our evaluations demonstrate that QeiHaN reduces memory movement by 67%, leading to a 4.2× speedup in execution time and a 3.5× reduction in energy consumption compared to conventional baseline architectures. Lastly, we propose Lama, a lightweight memory access mechanism that enhances lookup table (LUT)-based processing-in-memory (PuM) architectures by enabling parallel, column-independent accesses within DRAM mats, supporting up to 8-bit integer SIMD operations for large-scale models. The experimental results show that Lama significantly reduces memory commands for SIMD operations compared to the state-of-the-art PuM techniques. We further leverage Lama to design LamaAccel, an HBM-based large language model (LLM) accelerator that executes efficiently without modifying DRAM timing parameters. LamaAccel outperforms GPUs by up to 19×, achieving substantial energy savings in low-precision layers. The proposed techniques collectively reduce data movement, optimize memory utilization, and improve computational efficiency. Our findings demonstrate that memory-centric approaches can significantly enhance DNN acceleration, offering scalable and energy-efficient solutions for next-generation AI systems. |
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