Reliability in the face of variability in nanometer embedded memories

In this thesis, we have investigated the impact of parametric variations on the behaviour of one performance-critical processor structure - embedded memories. As variations manifest as a spread in power and performance, as a first step, we propose a novel modeling methodology that helps evaluate the...

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Detalles Bibliográficos
Autor: Ganapathy, Shrikanth
Tipo de recurso: tesis doctoral
Fecha de publicación:2014
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/95286
Acceso en línea:https://hdl.handle.net/2117/95286
https://dx.doi.org/10.5821/dissertation-2117-95286
Access Level:acceso abierto
Palabra clave:Arquitectura d'ordinadors
Àrees temàtiques de la UPC::Informàtica
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spelling Reliability in the face of variability in nanometer embedded memoriesGanapathy, ShrikanthArquitectura d'ordinadorsÀrees temàtiques de la UPC::InformàticaIn this thesis, we have investigated the impact of parametric variations on the behaviour of one performance-critical processor structure - embedded memories. As variations manifest as a spread in power and performance, as a first step, we propose a novel modeling methodology that helps evaluate the impact of circuit-level optimizations on architecture-level design choices. Choices made at the design-stage ensure conflicting requirements from higher-levels are decoupled. We then complement such design-time optimizations with a runtime mechanism that takes advantage of adaptive body-biasing to lower power whilst improving performance in the presence of variability. Our proposal uses a novel fully-digital variation tracking hardware using embedded DRAM (eDRAM) cells to monitor run-time changes in cache latency and leakage. A special fine-grain body-bias generator uses the measurements to generate an optimal body-bias that is needed to meet the required yield targets. A novel variation-tolerant and soft-error hardened eDRAM cell is also proposed as an alternate candidate for replacing existing SRAM-based designs in latency critical memory structures. In the ultra low-power domain where reliable operation is limited by the minimum voltage of operation (Vddmin), we analyse the impact of failures on cache functional margin and functional yield. Towards this end, we have developed a fully automated tool (INFORMER) capable of estimating memory-wide metrics such as power, performance and yield accurately and rapidly. Using the developed tool, we then evaluate the #effectiveness of a new class of hybrid techniques in improving cache yield through failure prevention and correction. Having a holistic perspective of memory-wide metrics helps us arrive at design-choices optimized simultaneously for multiple metrics needed for maintaining lifetime requirements.Universitat Politècnica de CatalunyaCanal Corretger, RamonGonzález Colás, Antonio MaríaRubio Sola, Jose Antonio20142014-04-2820142014-06-04doctoral thesishttp://purl.org/coar/resource_type/c_db06VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/doctoralThesisapplication/pdfhttps://hdl.handle.net/2117/95286https://dx.doi.org/10.5821/dissertation-2117-95286reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/952862026-05-27T15:37:01Z
dc.title.none.fl_str_mv Reliability in the face of variability in nanometer embedded memories
title Reliability in the face of variability in nanometer embedded memories
spellingShingle Reliability in the face of variability in nanometer embedded memories
Ganapathy, Shrikanth
Arquitectura d'ordinadors
Àrees temàtiques de la UPC::Informàtica
title_short Reliability in the face of variability in nanometer embedded memories
title_full Reliability in the face of variability in nanometer embedded memories
title_fullStr Reliability in the face of variability in nanometer embedded memories
title_full_unstemmed Reliability in the face of variability in nanometer embedded memories
title_sort Reliability in the face of variability in nanometer embedded memories
dc.creator.none.fl_str_mv Ganapathy, Shrikanth
author Ganapathy, Shrikanth
author_facet Ganapathy, Shrikanth
author_role author
dc.contributor.none.fl_str_mv Canal Corretger, Ramon
González Colás, Antonio María
Rubio Sola, Jose Antonio
dc.subject.none.fl_str_mv Arquitectura d'ordinadors
Àrees temàtiques de la UPC::Informàtica
topic Arquitectura d'ordinadors
Àrees temàtiques de la UPC::Informàtica
description In this thesis, we have investigated the impact of parametric variations on the behaviour of one performance-critical processor structure - embedded memories. As variations manifest as a spread in power and performance, as a first step, we propose a novel modeling methodology that helps evaluate the impact of circuit-level optimizations on architecture-level design choices. Choices made at the design-stage ensure conflicting requirements from higher-levels are decoupled. We then complement such design-time optimizations with a runtime mechanism that takes advantage of adaptive body-biasing to lower power whilst improving performance in the presence of variability. Our proposal uses a novel fully-digital variation tracking hardware using embedded DRAM (eDRAM) cells to monitor run-time changes in cache latency and leakage. A special fine-grain body-bias generator uses the measurements to generate an optimal body-bias that is needed to meet the required yield targets. A novel variation-tolerant and soft-error hardened eDRAM cell is also proposed as an alternate candidate for replacing existing SRAM-based designs in latency critical memory structures. In the ultra low-power domain where reliable operation is limited by the minimum voltage of operation (Vddmin), we analyse the impact of failures on cache functional margin and functional yield. Towards this end, we have developed a fully automated tool (INFORMER) capable of estimating memory-wide metrics such as power, performance and yield accurately and rapidly. Using the developed tool, we then evaluate the #effectiveness of a new class of hybrid techniques in improving cache yield through failure prevention and correction. Having a holistic perspective of memory-wide metrics helps us arrive at design-choices optimized simultaneously for multiple metrics needed for maintaining lifetime requirements.
publishDate 2014
dc.date.none.fl_str_mv 2014
2014-04-28
2014
2014-06-04
dc.type.none.fl_str_mv doctoral thesis
http://purl.org/coar/resource_type/c_db06
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/doctoralThesis
format doctoralThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/95286
https://dx.doi.org/10.5821/dissertation-2117-95286
url https://hdl.handle.net/2117/95286
https://dx.doi.org/10.5821/dissertation-2117-95286
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300724

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