An adpative ΣΔ modulator for multi-standard hand-held wireless devices

This paper describes the design and experimental characterization of a 130-nm CMOS cascade ΣΔ modulator intended for multi-standard wireless telecom systems. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt its performance to different...

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Detalles Bibliográficos
Autores: Morgado, Alonso, Río, Rocío del, Rosa, José M. de la
Tipo de recurso: artículo
Fecha de publicación:2007
País:España
Institución:Consejo Superior de Investigaciones Científicas (CSIC)
Repositorio:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:digital.csic.es:10261/3764
Acceso en línea:http://hdl.handle.net/10261/3764
Access Level:acceso abierto
Palabra clave:Adaptive Circuits
Sigma-Delta Modulators
Multi-Standard wireless devices
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spelling An adpative ΣΔ modulator for multi-standard hand-held wireless devicesMorgado, AlonsoRío, Rocío delRosa, José M. de laAdaptive CircuitsSigma-Delta ModulatorsMulti-Standard wireless devicesThis paper describes the design and experimental characterization of a 130-nm CMOS cascade ΣΔ modulator intended for multi-standard wireless telecom systems. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt its performance to different standard specifications with optimized power dissipation. Measurements show a correct operation for GSM/Bluetooth/WCDMA standards, featuring a dynamic range of 86.7/81.0/63.3dB and a peak signal-to-(noise+distortion) ratio of 74.0/68.4/52.8dB within 200kHz/1MHz/4MHz, respectively. The power consumption is 25.2/25.0/44.5mW, of which 11.0/10.5/24.8 are due to the analog part of the circuit.This work has been supported by the Spanish Ministry of Science and Education (contract TEC2004-01752/MIC) and the Spanish Ministry of Industry, Tourism and Commerce FIT-330100-2006-134 SPIRIT).Peer reviewedInstitute of Electrical and Electronics Engineers200820082007info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_65011251380 bytesapplication/pdfhttp://hdl.handle.net/10261/3764reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)Inglésinfo:eu-repo/semantics/openAccessoai:digital.csic.es:10261/37642026-05-22T06:33:51Z
dc.title.none.fl_str_mv An adpative ΣΔ modulator for multi-standard hand-held wireless devices
title An adpative ΣΔ modulator for multi-standard hand-held wireless devices
spellingShingle An adpative ΣΔ modulator for multi-standard hand-held wireless devices
Morgado, Alonso
Adaptive Circuits
Sigma-Delta Modulators
Multi-Standard wireless devices
title_short An adpative ΣΔ modulator for multi-standard hand-held wireless devices
title_full An adpative ΣΔ modulator for multi-standard hand-held wireless devices
title_fullStr An adpative ΣΔ modulator for multi-standard hand-held wireless devices
title_full_unstemmed An adpative ΣΔ modulator for multi-standard hand-held wireless devices
title_sort An adpative ΣΔ modulator for multi-standard hand-held wireless devices
dc.creator.none.fl_str_mv Morgado, Alonso
Río, Rocío del
Rosa, José M. de la
author Morgado, Alonso
author_facet Morgado, Alonso
Río, Rocío del
Rosa, José M. de la
author_role author
author2 Río, Rocío del
Rosa, José M. de la
author2_role author
author
dc.subject.none.fl_str_mv Adaptive Circuits
Sigma-Delta Modulators
Multi-Standard wireless devices
topic Adaptive Circuits
Sigma-Delta Modulators
Multi-Standard wireless devices
description This paper describes the design and experimental characterization of a 130-nm CMOS cascade ΣΔ modulator intended for multi-standard wireless telecom systems. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt its performance to different standard specifications with optimized power dissipation. Measurements show a correct operation for GSM/Bluetooth/WCDMA standards, featuring a dynamic range of 86.7/81.0/63.3dB and a peak signal-to-(noise+distortion) ratio of 74.0/68.4/52.8dB within 200kHz/1MHz/4MHz, respectively. The power consumption is 25.2/25.0/44.5mW, of which 11.0/10.5/24.8 are due to the analog part of the circuit.
publishDate 2007
dc.date.none.fl_str_mv 2007
2008
2008
dc.type.none.fl_str_mv info:eu-repo/semantics/article
http://purl.org/coar/resource_type/c_6501
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dc.identifier.none.fl_str_mv http://hdl.handle.net/10261/3764
url http://hdl.handle.net/10261/3764
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 1251380 bytes
application/pdf
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC
instname:Consejo Superior de Investigaciones Científicas (CSIC)
instname_str Consejo Superior de Investigaciones Científicas (CSIC)
reponame_str DIGITAL.CSIC. Repositorio Institucional del CSIC
collection DIGITAL.CSIC. Repositorio Institucional del CSIC
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repository.mail.fl_str_mv
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