The analog front end for FastRICH: an ASIC for the LHCb RICH detector upgrade

This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout detectors like Photomultiplier Tubes to be used at the LHC Run 4 and Silicon Photomultipliers candidates for Run 5. The...

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Detalles Bibliográficos
Autores: Manera Escalero, Rafel, Ballabriga, R., Mauricio, J., Kaplon, J., Paterno, A., Bandi, F., Gómez, Sergio, Pulli, A., Portero, S., Silva, J., Keizer, F., d'Ambrosio, C., Campbell, Michael, Gascón Fora, David
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2024
País:España
Institución:Universidad de Barcelona
Repositorio:Dipòsit Digital de la UB
OAI Identifier:oai:diposit.ub.edu:2445/220549
Acceso en línea:https://hdl.handle.net/2445/220549
Access Level:acceso abierto
Palabra clave:Detectors
Circuits electrònics
Radiació
Electronic circuits
Radiation
Descripción
Sumario:This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout detectors like Photomultiplier Tubes to be used at the LHC Run 4 and Silicon Photomultipliers candidates for Run 5. The front-end (FE) stage has an input impedance below 50 Ω and an input dynamic range from 5 μA to 5 mA with a power consumption of ∼5 mW/channel. The chip includes a Leading Edge Comparator (LED) and a Constant Fraction Discriminator (CFD) for time pick-off and a Time-to-Digital Converter (TDC) for digitization. 

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