Improving real-time guarantees of cache coherence and advanced interconnections in real-time systems
(English) The dissertation, research on enhancing timing predictability and performance for Critical Real-Time Embedded Systems (CRTES), focusing on Multi-Processor Systems on Chip (MPSoCs). CRTES are essential in critical domains like automotive and avionics, where complex functionalities and high...
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| Formato: | tesis doctoral |
| Fecha de publicación: | 2025 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/429994 |
| Acesso em linha: | https://hdl.handle.net/2117/429994 https://dx.doi.org/10.5821/dissertation-2117-429994 |
| Access Level: | acceso abierto |
| Palavra-chave: | Cache Coherence Interconnections Real-Time Predictability Vector Extensions Critical Embedded Systems Critical Real-Time Embedded Systems Hardware Event Monitors 004 - Informàtica Àrees temàtiques de la UPC::Informàtica |
| Resumo: | (English) The dissertation, research on enhancing timing predictability and performance for Critical Real-Time Embedded Systems (CRTES), focusing on Multi-Processor Systems on Chip (MPSoCs). CRTES are essential in critical domains like automotive and avionics, where complex functionalities and high performance are increasingly required for operations such as AI and multi-sensor data processing. However, MPSoCs face significant timing verification and validation (V&V) challenges, especially related to shared resources like caches and interconnects, which can introduce unpredictable delays. This thesis addresses three core areas to improve CRTES predictability: cache coherence, interconnection predictability, and application performance through vector extensions. Cache Coherence: In MPSoCs, cache coherence protocols ensure consistent data across multiple cores, but shared caches introduce contention that affects timing predictability. Traditional approaches to improving coherence often involve modifying protocols, a costly and complex task. This thesis takes an alternative approach by leveraging hardware event monitors (HEMs) to observe cache contention, providing valuable data for timing V&V without altering existing protocols. This methodology is applied to commercial MPSoCs like the NXP T1040 and T2080, which are widely used in real-time domains.On another note, the Remote Protocol-Contention Tracking (RPCT) method is proposed, which enables fine-grained tracking of delays due to inter-core contention, offering insights into cache coherence impacts on software predictability and informing developers on optimization strategies. Additionally, the thesis proposes a novel Multiple HEM Validation (MHV) method to improve the accuracy of contention measurements by validating HEM reliability through inter-HEM relationships, mitigating known issues with single-event HEM inaccuracies. Interconnections: MPSoCs rely on point-to-point (P2P) communication protocols like AXI4 for data transfer between cores, but the standard AXI protocol lacks timing constraints, making it unpredictable under real-time requirements. Addressing this, this thesis introduces AXI4 Real-Time (AXI4RT), an extension to the AXI protocol that specifies timing parameters to control the duration of transactions between manager and subordinate interfaces. By defining timing guarantees directly within the protocol, AXI4RT ensures predictable communication, enhancing system reliability for real-time applications. Additionally, this thesis provides some initial steps for contention tracking on modern AXI5 interconnects by doing an in-depth analysis how can contention be tracked with currently available HEMs and proposing some HEMs that could improve this tracking. Application Performance with Vector Extensions: To meet growing performance demands in CRTES, MPSoCs often use GPUs and custom accelerators, but these present certification challenges due to their complexity and unpredictable timing. This thesis explores using vector extensions (VExt) as an alternative. Single Instruction Multiple Data (SIMD) processing units are already available in many embedded processors, which perform parallel operations on multiple data elements, effectively improving data processing speeds. Unlike GPUs, VExt are integrated within processors and comply with high-integrity system standards, making them easier to certify. The thesis provides an analysis of VExt in COTS processors like NVIDIA’s AGX Xavier and show their potential to enhance performance while maintaining compliance with standards such as MISRA-C. In summary, this thesis advances the state-of-the-art in CRTES predictability, presenting solutions that ensure more reliable timing for complex embedded systems in safety-critical applications. By addressing cache coherence, interconnect timing, and performance, this thesis provides tools and methodologies for better timing analysis, enabling MPSoCs to improve real-time guarantees. |
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