Software caching techniques and hardware optimizations for on-chip local memories
Despite the fact that the most viable L1 memories in processors are caches, on-chip local memories have been a great topic of consideration lately. Local memories are an interesting design option due to their many benefits: less area occupancy, reduced energy consumption and fast and constant access...
| Autor: | |
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| Tipo de recurso: | tesis doctoral |
| Estado: | Versión publicada |
| Fecha de publicación: | 2012 |
| País: | España |
| Institución: | CBUC, CESCA |
| Repositorio: | TDR. Tesis Doctorales en Red |
| OAI Identifier: | oai:www.tdx.cat:10803/83598 |
| Acceso en línea: | http://hdl.handle.net/10803/83598 https://dx.doi.org/10.5821/dissertation-2117-94621 |
| Access Level: | acceso abierto |
| Palabra clave: | computer architecture high performance computing on-chip local memories software cache DMA multicores 004 |
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Software caching techniques and hardware optimizations for on-chip local memories |
| title |
Software caching techniques and hardware optimizations for on-chip local memories |
| spellingShingle |
Software caching techniques and hardware optimizations for on-chip local memories Vujic, Nikola computer architecture high performance computing on-chip local memories software cache DMA multicores 004 |
| title_short |
Software caching techniques and hardware optimizations for on-chip local memories |
| title_full |
Software caching techniques and hardware optimizations for on-chip local memories |
| title_fullStr |
Software caching techniques and hardware optimizations for on-chip local memories |
| title_full_unstemmed |
Software caching techniques and hardware optimizations for on-chip local memories |
| title_sort |
Software caching techniques and hardware optimizations for on-chip local memories |
| dc.creator.none.fl_str_mv |
Vujic, Nikola |
| author |
Vujic, Nikola |
| author_facet |
Vujic, Nikola |
| author_role |
author |
| dc.contributor.none.fl_str_mv |
Gonzàlez Tallada, Marc Ayguadé i Parra, Eduard Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.subject.none.fl_str_mv |
computer architecture high performance computing on-chip local memories software cache DMA multicores 004 |
| topic |
computer architecture high performance computing on-chip local memories software cache DMA multicores 004 |
| description |
Despite the fact that the most viable L1 memories in processors are caches, on-chip local memories have been a great topic of consideration lately. Local memories are an interesting design option due to their many benefits: less area occupancy, reduced energy consumption and fast and constant access time. These benefits are especially interesting for the design of modern multicore processors since power and latency are important assets in computer architecture today. Also, local memories do not generate coherency traffic which is important for the scalability of the multicore systems. Unfortunately, local memories have not been well accepted in modern processors yet, mainly due to their poor programmability. Systems with on-chip local memories do not have hardware support for transparent data transfers between local and global memories, and thus ease of programming is one of the main impediments for the broad acceptance of those systems. This thesis addresses software and hardware optimizations regarding the programmability, and the usage of the on-chip local memories in the context of both single-core and multicore systems. Software optimizations are related to the software caching techniques. Software cache is a robust approach to provide the user with a transparent view of the memory architecture; but this software approach can suffer from poor performance. In this thesis, we start optimizing traditional software cache by proposing a hierarchical, hybrid software-cache architecture. Afterwards, we develop few optimizations in order to speedup our hybrid software cache as much as possible. As the result of the software optimizations we obtain that our hybrid software cache performs from 4 to 10 times faster than traditional software cache on a set of NAS parallel benchmarks. We do not stop with software caching. We cover some other aspects of the architectures with on-chip local memories, such as the quality of the generated code and its correspondence with the quality of the buffer management in local memories, in order to improve performance of these architectures. Therefore, we run our research till we reach the limit in software and start proposing optimizations on the hardware level. Two hardware proposals are presented in this thesis. One is about relaxing alignment constraints imposed in the architectures with on-chip local memories and the other proposal is about accelerating the management of local memories by providing hardware support for the majority of actions performed in our software cache. |
| publishDate |
2012 |
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2012 2012 2012 |
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info:eu-repo/semantics/doctoralThesis info:eu-repo/semantics/publishedVersion |
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doctoralThesis |
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publishedVersion |
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http://hdl.handle.net/10803/83598 https://dx.doi.org/10.5821/dissertation-2117-94621 |
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http://hdl.handle.net/10803/83598 https://dx.doi.org/10.5821/dissertation-2117-94621 |
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Inglés |
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Inglés |
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http://creativecommons.org/licenses/by-nc/3.0/es/ info:eu-repo/semantics/openAccess |
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http://creativecommons.org/licenses/by-nc/3.0/es/ |
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openAccess |
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159 p. application/pdf application/pdf |
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Universitat Politècnica de Catalunya |
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Universitat Politècnica de Catalunya |
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TDX (Tesis Doctorals en Xarxa) reponame:TDR. Tesis Doctorales en Red instname:CBUC, CESCA |
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CBUC, CESCA |
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TDR. Tesis Doctorales en Red |
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TDR. Tesis Doctorales en Red |
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1869422344168013824 |
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Software caching techniques and hardware optimizations for on-chip local memoriesVujic, Nikolacomputer architecturehigh performance computingon-chip local memoriessoftware cacheDMAmulticores004Despite the fact that the most viable L1 memories in processors are caches, on-chip local memories have been a great topic of consideration lately. Local memories are an interesting design option due to their many benefits: less area occupancy, reduced energy consumption and fast and constant access time. These benefits are especially interesting for the design of modern multicore processors since power and latency are important assets in computer architecture today. Also, local memories do not generate coherency traffic which is important for the scalability of the multicore systems. Unfortunately, local memories have not been well accepted in modern processors yet, mainly due to their poor programmability. Systems with on-chip local memories do not have hardware support for transparent data transfers between local and global memories, and thus ease of programming is one of the main impediments for the broad acceptance of those systems. This thesis addresses software and hardware optimizations regarding the programmability, and the usage of the on-chip local memories in the context of both single-core and multicore systems. Software optimizations are related to the software caching techniques. Software cache is a robust approach to provide the user with a transparent view of the memory architecture; but this software approach can suffer from poor performance. In this thesis, we start optimizing traditional software cache by proposing a hierarchical, hybrid software-cache architecture. Afterwards, we develop few optimizations in order to speedup our hybrid software cache as much as possible. As the result of the software optimizations we obtain that our hybrid software cache performs from 4 to 10 times faster than traditional software cache on a set of NAS parallel benchmarks. We do not stop with software caching. We cover some other aspects of the architectures with on-chip local memories, such as the quality of the generated code and its correspondence with the quality of the buffer management in local memories, in order to improve performance of these architectures. Therefore, we run our research till we reach the limit in software and start proposing optimizations on the hardware level. Two hardware proposals are presented in this thesis. One is about relaxing alignment constraints imposed in the architectures with on-chip local memories and the other proposal is about accelerating the management of local memories by providing hardware support for the majority of actions performed in our software cache.Malgrat les memòries cau encara son el component basic pel disseny del subsistema de memòria, les memòries locals han esdevingut una alternativa degut a les seves característiques pel que fa a l’ocupació d’àrea, el seu consum energètic i el seu rendiment amb un temps d’accés ràpid i constant. Aquestes característiques son d’especial interès quan les properes arquitectures multi-nucli estan limitades pel consum de potencia i la latència del subsistema de memòria.Les memòries locals pateixen de limitacions respecte la complexitat en la seva programació, fet que dificulta la seva introducció en arquitectures multi-nucli, tot i els avantatges esmentats anteriorment. Aquesta tesi presenta un seguit de solucions basades en programari i maquinari específicament dissenyat per resoldre aquestes limitacions.Les optimitzacions del programari estan basades amb tècniques d'emmagatzematge de memòria cau suportades per llibreries especifiques. La memòria cau per programari és un sòlid mètode per proporcionar a l'usuari una visió transparent de l'arquitectura, però aquest enfocament pot patir d'un rendiment deficient. En aquesta tesi, es proposa una estructura jeràrquica i híbrida. Posteriorment, desenvolupem optimitzacions per tal d'accelerar l’execució del programari que suporta el disseny de la memòria cau. Com a resultat de les optimitzacions realitzades, obtenim que el nostre disseny híbrid es comporta de 4 a 10 vegades més ràpid que una implementació tradicional de memòria cau sobre un conjunt d’aplicacions de referencia, com son els “NAS parallel benchmarks”.El treball de tesi inclou altres aspectes de les arquitectures amb memòries locals, com ara la qualitat del codi generat i la seva correspondència amb la qualitat de la gestió de memòria intermèdia en les memòries locals, per tal de millorar el rendiment d'aquestes arquitectures. La tesi desenvolupa propostes basades estrictament en el disseny de nou maquinari per tal de millorar el rendiment de les memòries locals quan ja no es possible realitzar mes optimitzacions en el programari. En particular, la tesi presenta dues propostes de maquinari: una relaxa les restriccions imposades per les memòries locals respecte l’alineament de dades, l’altra introdueix maquinari específic per accelerar les operacions mes usuals sobre les memòries locals.DOCTORAT EN ARQUITECTURA DE COMPUTADORS (Pla 2007)Universitat Politècnica de CatalunyaGonzàlez Tallada, MarcAyguadé i Parra, EduardUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors201220122012info:eu-repo/semantics/doctoralThesisinfo:eu-repo/semantics/publishedVersion159 p.application/pdfapplication/pdfhttp://hdl.handle.net/10803/83598https://dx.doi.org/10.5821/dissertation-2117-94621TDX (Tesis Doctorals en Xarxa)reponame:TDR. Tesis Doctorales en Redinstname:CBUC, CESCAInglésL'accés als continguts d'aquesta tesi queda condicionat a l'acceptació de les condicions d'ús establertes per la següent llicència Creative Commons: http://creativecommons.org/licenses/by-nc/3.0/es/http://creativecommons.org/licenses/by-nc/3.0/es/info:eu-repo/semantics/openAccessoai:www.tdx.cat:10803/835982026-06-14T12:46:07Z |
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15,300719 |