Digital test for the extraction of integrator leakage in first- and second-order ΣΔ modulators
This paper proposes a digital technique to evaluate the integrator leakage within 1st and 2nd order ΣΔ modulators. Integrator leakage is known to be related to the converter precision and belongs to the basic set of design specifications. The technique proposed here involves very few hardware, which...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2004 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/77103 |
| Acceso en línea: | https://hdl.handle.net/11441/77103 https://doi.org/10.1049/ip-cds:20040558(410)%20151 |
| Access Level: | acceso abierto |
| Palabra clave: | ΣΔ modulators Testability BIST |
| Sumario: | This paper proposes a digital technique to evaluate the integrator leakage within 1st and 2nd order ΣΔ modulators. Integrator leakage is known to be related to the converter precision and belongs to the basic set of design specifications. The technique proposed here involves very few hardware, which makes it specially suitable for Built-In Self-Test (BIST) implementation. Moreover, the integrator leakage evaluation allows its digital correction in cascaded modulators. |
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