Design and physical implementation of a distributed clock module for an EtherCAT slave controller
This report covers the development of the Distributed Clock module, following every design stage until a manufacturable layout was achieved. The module was designed independently of the main chip, so it does not explain deeply external blocks. Even so, an introduction to the EtherCAT protocol and th...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/442487 |
| Acceso en línea: | https://hdl.handle.net/2117/442487 |
| Access Level: | acceso abierto |
| Palabra clave: | Integrated circuits -- Design and construction Microelectronics Device drivers (Computer programs) Circuits integrats -- Disseny i construcció Microelectrònica Programes controladors Àrees temàtiques de la UPC::Enginyeria electrònica |
| Sumario: | This report covers the development of the Distributed Clock module, following every design stage until a manufacturable layout was achieved. The module was designed independently of the main chip, so it does not explain deeply external blocks. Even so, an introduction to the EtherCAT protocol and the EtherCAT Slave Controller, together with its sub functions, are included. Also, a thorough explanation of the distributed clock is also provided to ensure a complete understanding of how this logic block operates. In addition, an extend explanation of some methodologies were developed for certain chip functions, such as drift, which was refined to give the system the best possible adaptability. The classical digital‑chip flow was followed: writing RTL code, validating it with testbenches, and synthesizing it into a gate‑level netlist using DC Compiler. Also, obtaining some preliminary estimations of area, power, and timing. The final step, the physical implementation or the chip layout design was completed with Encounter. The project concludes successfully with a final layout supported by solid area and power reports. Future steps are the integration of the module with the main chip and prepare the design for fabrication. |
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