OpenMP and OmpSS-2 parallelisation of LLMs
LLM inference on multicore CPUs is increasingly relevant for edge, cost-sensitive, and hybrid CPU-GPU deployments, yet a systematic comparison of shared-memory parallelisation frameworks applied directly to transformer inference kernels remains absent from the literature. This thesis is specifically...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2026 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:dnet:upcommonspor::f6b93c1275674d62af856404e8fe90cf |
| Acceso en línea: | https://hdl.handle.net/2117/462154 |
| Access Level: | acceso abierto |
| Palabra clave: | Parallel processing (Electronic computers) Parallel programming (Computer science) Llama 2 OpenMP OmpSs-2 benchmark model scales memory hierarchy Processament en paral·lel (Ordinadors) Programació en paral·lel (Informàtica) Àrees temàtiques de la UPC::Informàtica |
| Sumario: | LLM inference on multicore CPUs is increasingly relevant for edge, cost-sensitive, and hybrid CPU-GPU deployments, yet a systematic comparison of shared-memory parallelisation frameworks applied directly to transformer inference kernels remains absent from the literature. This thesis is specifically focused on parallelising llama2.c, a minimal C inference engine for Llama 2, using OpenMP fork-join, OpenMP taskloop, OpenMP task dataflow, and OmpSs-2 task dataflow, producing six implementation versions that are benchmarked across three AMD EPYC platforms (Zen 3, Zen 4 with 3D V-Cache, and Zen 5) at three model scales (15M, 110M, and 7B parameters). The evaluation covers thread scaling, NUMA-aware memory placement, and kernel-level timing analysis to identify where each parallelisation model succeeds and where synchronisation or task management overhead limits its effectiveness. The results reveal that the choice of parallelisation strategy interacts strongly with model scale and hardware memory hierarchy, and that more expressive task-based models do not universally outperform simpler loop-level approaches in memory-bandwidth-bound inference workloads. |
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