Understanding the thermal implications of multicore architectures
Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations by exploiting thread-level parallelism (TLP). In addition, it is a power a...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2007 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/101450 |
| Acceso en línea: | https://hdl.handle.net/2117/101450 https://dx.doi.org/10.1109/TPDS.2007.1092 |
| Access Level: | acceso abierto |
| Palabra clave: | Microprocessors Parallel processing (Electronic computers) Multicore architectures Dynamic thermal management Activity migration Dynamic voltage Frequency scaling Microprocessadors Processament en paral·lel (Ordinadors) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations by exploiting thread-level parallelism (TLP). In addition, it is a power and complexity-effective way of taking advantage of the huge number of transistors that can be integrated on a chip. On the other hand, today's higher than ever power densities have made temperature one of the main limitations of microprocessor evolution. Thermal management in multicore architectures is a fairly new area. Some works have addressed dynamic thermal management in bi/quad-core architectures. This work provides insight and explores different alternatives for thermal management in multicore architectures with 16 cores. Schemes employing both energy reduction and activity migration are explored and improvements for thread migration schemes are proposed. |
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