Comprehensive statistical analysis of random telegraph noise: Impact of gate voltage, temperature, and Bias time
This work presents a statistical analysis of Random Telegraph Noise (RTN) in nanoscale MOSFETs, from more than 13,000 traces measured under varying voltages, temperatures, and bias times on an array-based characterization chip. Using the Weighted Time Lag Plot (WTLP), we extracted the average number...
| Autores: | , , , , , , , , |
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| Formato: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2026 |
| País: | España |
| Recursos: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositorio: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/414257 |
| Acesso em linha: | http://hdl.handle.net/10261/414257 https://api.elsevier.com/content/abstract/scopus_id/105024920417 |
| Access Level: | acceso embargado |
| Palavra-chave: | CMOS Random telegraph noise Reliability Variability |
| Resumo: | This work presents a statistical analysis of Random Telegraph Noise (RTN) in nanoscale MOSFETs, from more than 13,000 traces measured under varying voltages, temperatures, and bias times on an array-based characterization chip. Using the Weighted Time Lag Plot (WTLP), we extracted the average number of detectable traps and the associated current step amplitudes. Results show that the average number of detectable traps increases with voltage and temperature but decreases after some bias time due to a transient trap population. The average current step amplitude grows with voltage and shows negligible dependence on temperature. These findings support improved RTN modeling and are relevant for both reliability analysis and cryptographic applications. |
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