A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

[EN] With the integration scale level reached in CMOS technology, memory systems provide a great storage capacity, but at the price of an augment in their fault rate. In this way, the probability of experiencing Single Cell Upsets or Multiple Cell Upsets have risen. Error Correction Codes (ECC) are...

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Autores: Gracia-Morán, Joaquín|||0000-0001-9715-8960, Saiz-Adalid, Luis-J.|||0000-0002-4868-2050, Baraza-Calvo, Juan-Carlos|||0000-0001-7692-2309, Gil Tomás, Daniel Antonio|||0000-0001-9225-1998, Gil, Pedro|||0000-0002-9364-7385
Tipo de recurso: artículo
Fecha de publicación:2024
País:España
Institución:Universitat Politècnica de València (UPV)
Repositorio:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
Idioma:inglés
OAI Identifier:oai:riunet.upv.es:10251/208922
Acceso en línea:https://riunet.upv.es/handle/10251/208922
Access Level:acceso abierto
Palabra clave:Adaptability
Error correction codes
Fault tolerance
Multiple bit errors
Single bit errors
Reliability
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
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repository_id_str
spelling A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data wordsGracia-Morán, Joaquín|||0000-0001-9715-8960Saiz-Adalid, Luis-J.|||0000-0002-4868-2050Baraza-Calvo, Juan-Carlos|||0000-0001-7692-2309Gil Tomás, Daniel Antonio|||0000-0001-9225-1998Gil, Pedro|||0000-0002-9364-7385AdaptabilityError correction codesFault toleranceMultiple bit errorsSingle bit errorsReliabilityARQUITECTURA Y TECNOLOGIA DE COMPUTADORES[EN] With the integration scale level reached in CMOS technology, memory systems provide a great storage capacity, but at the price of an augment in their fault rate. In this way, the probability of experiencing Single Cell Upsets or Multiple Cell Upsets have risen. Error Correction Codes (ECC) are broadly employed to protect memory systems. Though, the inclusion of an ECC in a computer system adds, in each memory word, some extra bits used to detect and/or correct errors. In addition, encoding and decoding circuitries must be added, introducing overheads in area, delay, and power consumption. Usually, when an ECC-based fault tolerance mechanism is designed, its fault tolerance properties cannot be modified. However, in some applications, current memory systems can suffer a variable fault rate during their operation. Thus, it seems very interesting that this mechanism would be able to adapt to these variable fault conditions. This work proposes an Adaptive Fault-Tolerant mechanism based on ECC. This mechanism can adapt to different fault conditions, being able to correct and/or detect single and multiple bits in error. The Adaptive Fault-Tolerant mechanism proposed uses a unique encoder, that is, it is not necessary to re-encode the data to change the error coverage.Proyecto PID2020-120271RB-I00 financiado por MCIN/AEI /10.13039/501100011033Institute of Electrical and Electronics EngineersDepartamento de Informática de Sistemas y ComputadoresInstituto Universitario de Tecnologías de la Información y ComunicacionesEscuela Técnica Superior de Ingeniería IndustrialEscuela Técnica Superior de Ingeniería InformáticaAGENCIA ESTATAL DE INVESTIGACIONRepositorio Institucional de la Universitat Politècnica de València Riunet20242024-05-01journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfapplication/pdfhttps://riunet.upv.es/handle/10251/208922reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valénciainstname:Universitat Politècnica de València (UPV)InglésengAgencia Estatal de Investigación http://dx.doi.org/10.13039/501100011033 Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020 PID2020-120271RB-I00 ACELERADORES BASADOS EN FPGAS PARA REDES NEURONALES PROFUNDAS SUFICIENTEMENTE CONFIABLES PARA SISTEMAS DE AUTOMOCIONopen accesshttp://purl.org/coar/access_right/c_abf2Reserva de todos los derechoshttp://rightsstatements.org/vocab/InC/1.0/info:eu-repo/semantics/openAccessoai:riunet.upv.es:10251/2089222026-06-13T07:49:27Z
dc.title.none.fl_str_mv A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
title A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
spellingShingle A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
Gracia-Morán, Joaquín|||0000-0001-9715-8960
Adaptability
Error correction codes
Fault tolerance
Multiple bit errors
Single bit errors
Reliability
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
title_short A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
title_full A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
title_fullStr A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
title_full_unstemmed A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
title_sort A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
dc.creator.none.fl_str_mv Gracia-Morán, Joaquín|||0000-0001-9715-8960
Saiz-Adalid, Luis-J.|||0000-0002-4868-2050
Baraza-Calvo, Juan-Carlos|||0000-0001-7692-2309
Gil Tomás, Daniel Antonio|||0000-0001-9225-1998
Gil, Pedro|||0000-0002-9364-7385
author Gracia-Morán, Joaquín|||0000-0001-9715-8960
author_facet Gracia-Morán, Joaquín|||0000-0001-9715-8960
Saiz-Adalid, Luis-J.|||0000-0002-4868-2050
Baraza-Calvo, Juan-Carlos|||0000-0001-7692-2309
Gil Tomás, Daniel Antonio|||0000-0001-9225-1998
Gil, Pedro|||0000-0002-9364-7385
author_role author
author2 Saiz-Adalid, Luis-J.|||0000-0002-4868-2050
Baraza-Calvo, Juan-Carlos|||0000-0001-7692-2309
Gil Tomás, Daniel Antonio|||0000-0001-9225-1998
Gil, Pedro|||0000-0002-9364-7385
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Departamento de Informática de Sistemas y Computadores
Instituto Universitario de Tecnologías de la Información y Comunicaciones
Escuela Técnica Superior de Ingeniería Industrial
Escuela Técnica Superior de Ingeniería Informática
AGENCIA ESTATAL DE INVESTIGACION
Repositorio Institucional de la Universitat Politècnica de València Riunet
dc.subject.none.fl_str_mv Adaptability
Error correction codes
Fault tolerance
Multiple bit errors
Single bit errors
Reliability
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
topic Adaptability
Error correction codes
Fault tolerance
Multiple bit errors
Single bit errors
Reliability
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
description [EN] With the integration scale level reached in CMOS technology, memory systems provide a great storage capacity, but at the price of an augment in their fault rate. In this way, the probability of experiencing Single Cell Upsets or Multiple Cell Upsets have risen. Error Correction Codes (ECC) are broadly employed to protect memory systems. Though, the inclusion of an ECC in a computer system adds, in each memory word, some extra bits used to detect and/or correct errors. In addition, encoding and decoding circuitries must be added, introducing overheads in area, delay, and power consumption. Usually, when an ECC-based fault tolerance mechanism is designed, its fault tolerance properties cannot be modified. However, in some applications, current memory systems can suffer a variable fault rate during their operation. Thus, it seems very interesting that this mechanism would be able to adapt to these variable fault conditions. This work proposes an Adaptive Fault-Tolerant mechanism based on ECC. This mechanism can adapt to different fault conditions, being able to correct and/or detect single and multiple bits in error. The Adaptive Fault-Tolerant mechanism proposed uses a unique encoder, that is, it is not necessary to re-encode the data to change the error coverage.
publishDate 2024
dc.date.none.fl_str_mv 2024
2024-05-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://riunet.upv.es/handle/10251/208922
url https://riunet.upv.es/handle/10251/208922
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.relation.none.fl_str_mv Agencia Estatal de Investigación http://dx.doi.org/10.13039/501100011033 Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020 PID2020-120271RB-I00 ACELERADORES BASADOS EN FPGAS PARA REDES NEURONALES PROFUNDAS SUFICIENTEMENTE CONFIABLES PARA SISTEMAS DE AUTOMOCION
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reserva de todos los derechos
http://rightsstatements.org/vocab/InC/1.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reserva de todos los derechos
http://rightsstatements.org/vocab/InC/1.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname:Universitat Politècnica de València (UPV)
instname_str Universitat Politècnica de València (UPV)
reponame_str RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
collection RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,81155

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