A Study of Low-Confidence Prefetches for Enhancing DRAM Row Buffer Locality
As high-performance computing (HPC) systems continue to grow in scale and complexity, memory performance has become a critical bottleneck. The widening gap between processor speed and DRAM access latency, commonly known as the memory wall, limits system throughput, while increasing data movement con...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/449738 |
| Acceso en línea: | https://hdl.handle.net/2117/449738 |
| Access Level: | acceso abierto |
| Palabra clave: | Computer storage devices Parallel processing (Electronic computers) memory hierarchy hardware prefetching DRAM row-buffer locality Ordinadors--Dispositius de memòria Processament en paral·lel (Ordinadors) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | As high-performance computing (HPC) systems continue to grow in scale and complexity, memory performance has become a critical bottleneck. The widening gap between processor speed and DRAM access latency, commonly known as the memory wall, limits system throughput, while increasing data movement contributes significantly to overall energy consumption. Hardware prefetching is a well-established and essential feature of modern high-performance processors, aiming to reduce memory latency. However, current designs typically discard low-confidence prefetches to avoid cache pollution and bandwidth contention, which means that potentially valuable predictive information is overlooked. This thesis proposes a novel architectural technique that repurposes these discarded low-confidence prefetches as speculative hints to guide memory controller behaviour. Rather than triggering cache fills, these predictions are used to improve DRAM row-buffer locality by preemptively activating memory rows likely to be accessed in the near future. The goal is to enhance memory access efficiency and increase prefetch coverage, without incurring the typical side effects of aggressive prefetching, such as bandwidth saturation or cache pollution. The proposed approach was evaluated using a trace-based, cycle-accurate simulator through both a simplified prototype and a realistic simulation model. Results show that low-confidence prefetches frequently correspond to future memory accesses and can be exploited to reduce memory access latency and improve overall efficiency. This work reveals that low-confidence prefetches can offer significant utility, introducing a new perspective on how hardware prefetching capabilities could be extended. |
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