Volume Resistive Switching in metallic perovskite oxides driven by the Metal-Insulator Transition
In recent years Resistive Random Access Memory (RRAM) is emerging as the most promising candidate to substitute the present Flash Technology in the non-volatile memory market. RRAM are based on the Resistive Switching (RS) effect, where a change in the resistance of the material can be reversibly in...
| Authors: | , , , , , , , , |
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| Format: | article |
| Status: | Versión aceptada para publicación |
| Publication Date: | 2017 |
| Country: | España |
| Institution: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repository: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/154888 |
| Online Access: | http://hdl.handle.net/10261/154888 |
| Access Level: | Open access |
| Keyword: | Resistive Switching Perovskite oxides Strongly correlated oxides R-RAM |
| Summary: | In recent years Resistive Random Access Memory (RRAM) is emerging as the most promising candidate to substitute the present Flash Technology in the non-volatile memory market. RRAM are based on the Resistive Switching (RS) effect, where a change in the resistance of the material can be reversibly induced upon the application of an electric field. In this sense, strongly correlated complex oxides present unique intrinsic properties and extreme sensitivity to external perturbations, which make them suitable for the nanoelectronics of the future. In particular, metallic complex oxides displaying metal-insulator transition (MIT) are very attractive materials for applications and are barely explored as RS active elements. In this work, we analyze the RS behavior of three different families of metallic perovskites: La0.8Sr0.2MnO3, YBa2Cu3O7-δ and NdNiO3. We demonstrate that these mixed electronic-ionic conductors undergo a metal-insulator transition upon the application of an electric field, being able to transform the bulk volume. This volume RS is different in nature from interfacial or filamentary type and opens new possibilities of robust device design. As an example, we present a proof-of-principle result from a 3-Terminal configuration with multilevel memory states. |
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