Embedded and DSP design tools integration for Xilinx FPGA development

The aim of this projecte de final de master is to design a firmware with VHDL and the Matlab System Generator for Xilinx DSP of a test application, which mixes several of the Xilinx tools to create the design. The target FPGA is a Spartan 6 from a SP605 test board. In addition, this memory contains...

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Detalles Bibliográficos
Autor: Estevadeordal Serra, Carles
Tipo de recurso: tesis de maestría
Fecha de publicación:2010
País:España
Institución:Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya)
Repositorio:Recercat. Dipósit de la Recerca de Catalunya
OAI Identifier:oai:recercat.cat:20.500.14342/2776
Acceso en línea:http://hdl.handle.net/20.500.14342/2776
Access Level:acceso abierto
Palabra clave:Dispositius lògics programables -- TFM
Matrius de portes programables per l'usuari -- TFM
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spelling Embedded and DSP design tools integration for Xilinx FPGA developmentEstevadeordal Serra, CarlesDispositius lògics programables -- TFMMatrius de portes programables per l'usuari -- TFM00462The aim of this projecte de final de master is to design a firmware with VHDL and the Matlab System Generator for Xilinx DSP of a test application, which mixes several of the Xilinx tools to create the design. The target FPGA is a Spartan 6 from a SP605 test board. In addition, this memory contains the main characteristics of the firmware design, a description of the tools used and the methodologies available to create the Firmware. Furthermore, it provides some theoric background and in some cases, it is useful as a guide to implement a similar solution to the one proposed. Furthermore, there is a description of the findings in the System Generator design field and also with the interaction in the Xilinx FPGA design flow. There have been described the tests which were performed to ensure the correctness of the design.Universitat Ramon Llull. La Salle2010info:eu-repo/semantics/masterThesis82 p.http://hdl.handle.net/20.500.14342/2776reponame:Recercat. Dipósit de la Recerca de Catalunyainstname:Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya)InglésENG TFM MUEXT;1862Attribution-NonCommercial-NoDerivatives 4.0 International© Escola Tècnica Superior d'Enginyeria La Sallehttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/openAccessoai:recercat.cat:20.500.14342/27762026-05-29T05:05:01Z
dc.title.none.fl_str_mv Embedded and DSP design tools integration for Xilinx FPGA development
title Embedded and DSP design tools integration for Xilinx FPGA development
spellingShingle Embedded and DSP design tools integration for Xilinx FPGA development
Estevadeordal Serra, Carles
Dispositius lògics programables -- TFM
Matrius de portes programables per l'usuari -- TFM
004
62
title_short Embedded and DSP design tools integration for Xilinx FPGA development
title_full Embedded and DSP design tools integration for Xilinx FPGA development
title_fullStr Embedded and DSP design tools integration for Xilinx FPGA development
title_full_unstemmed Embedded and DSP design tools integration for Xilinx FPGA development
title_sort Embedded and DSP design tools integration for Xilinx FPGA development
dc.creator.none.fl_str_mv Estevadeordal Serra, Carles
author Estevadeordal Serra, Carles
author_facet Estevadeordal Serra, Carles
author_role author
dc.contributor.none.fl_str_mv Universitat Ramon Llull. La Salle
dc.subject.none.fl_str_mv Dispositius lògics programables -- TFM
Matrius de portes programables per l'usuari -- TFM
004
62
topic Dispositius lògics programables -- TFM
Matrius de portes programables per l'usuari -- TFM
004
62
description The aim of this projecte de final de master is to design a firmware with VHDL and the Matlab System Generator for Xilinx DSP of a test application, which mixes several of the Xilinx tools to create the design. The target FPGA is a Spartan 6 from a SP605 test board. In addition, this memory contains the main characteristics of the firmware design, a description of the tools used and the methodologies available to create the Firmware. Furthermore, it provides some theoric background and in some cases, it is useful as a guide to implement a similar solution to the one proposed. Furthermore, there is a description of the findings in the System Generator design field and also with the interaction in the Xilinx FPGA design flow. There have been described the tests which were performed to ensure the correctness of the design.
publishDate 2010
dc.date.none.fl_str_mv 2010
dc.type.none.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
dc.identifier.none.fl_str_mv http://hdl.handle.net/20.500.14342/2776
url http://hdl.handle.net/20.500.14342/2776
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv ENG TFM MUEXT;1862
dc.rights.none.fl_str_mv Attribution-NonCommercial-NoDerivatives 4.0 International
© Escola Tècnica Superior d'Enginyeria La Salle
http://creativecommons.org/licenses/by-nc-nd/4.0/
info:eu-repo/semantics/openAccess
rights_invalid_str_mv Attribution-NonCommercial-NoDerivatives 4.0 International
© Escola Tècnica Superior d'Enginyeria La Salle
http://creativecommons.org/licenses/by-nc-nd/4.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 82 p.
dc.source.none.fl_str_mv reponame:Recercat. Dipósit de la Recerca de Catalunya
instname:Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya)
instname_str Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya)
reponame_str Recercat. Dipósit de la Recerca de Catalunya
collection Recercat. Dipósit de la Recerca de Catalunya
repository.name.fl_str_mv
repository.mail.fl_str_mv
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