Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas

As the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques are being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable Gate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation step i...

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Detalles Bibliográficos
Autores: Sánchez González, Alberto, Castro Martín, Ángel de, Todorovich, Elías
Tipo de recurso: artículo
Fecha de publicación:2018
País:España
Institución:Universidad Autónoma de Madrid
Repositorio:Biblos-e Archivo. Repositorio Institucional de la UAM
Idioma:inglés
OAI Identifier:oai:repositorio.uam.es:10486/686680
Acceso en línea:http://hdl.handle.net/10486/686680
https://dx.doi.org/10.3390/electronics7100219
Access Level:acceso abierto
Palabra clave:Field programmable gate array
Fixed-point
Floating-point
Hardware-in-the-loop
Real-time emulation
Informática
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spelling Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgasSánchez González, AlbertoCastro Martín, Ángel deTodorovich, ElíasField programmable gate arrayFixed-pointFloating-pointHardware-in-the-loopReal-time emulationInformáticaAs the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques are being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable Gate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation step is reduced, the incremental values for the state variables are reduced proportionally, increasing the difference between the current value of the state variable and its increments. This difference can lead to numerical resolution issues when both magnitudes cannot be stored simultaneously in the state variable. FPGA-based HIL systems generally use 32-bit floating-point due to hardware and timing restrictions but they may suffer from these resolution problems. This paper explores the limits of 32-bit floating-point arithmetics in the context of hardware-in-the-loop systems, and how a larger format can be used to avoid resolution problems. The consequences in terms of hardware resources and running frequency are also explored. Although the conclusions reached in this work can be applied to any digital device, they can be directly used in the field of FPGAs, where the designer can easily use custom floating-point arithmetics.This research was funded by Spanish Ministerio de Economía y Competitividad grant number TEC2013-43017-R.MDPI (Basel, Switzerland)Departamento de Tecnología Electrónica y de las ComunicacionesEscuela Politécnica Superior20182018-09-27research articlehttp://purl.org/coar/resource_type/c_2df8fbb1VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttp://hdl.handle.net/10486/686680https://dx.doi.org/10.3390/electronics7100219reponame:Biblos-e Archivo. Repositorio Institucional de la UAMinstname:Universidad Autónoma de MadridInglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:repositorio.uam.es:10486/6866802026-06-23T12:46:27Z
dc.title.none.fl_str_mv Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas
title Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas
spellingShingle Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas
Sánchez González, Alberto
Field programmable gate array
Fixed-point
Floating-point
Hardware-in-the-loop
Real-time emulation
Informática
title_short Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas
title_full Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas
title_fullStr Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas
title_full_unstemmed Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas
title_sort Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas
dc.creator.none.fl_str_mv Sánchez González, Alberto
Castro Martín, Ángel de
Todorovich, Elías
author Sánchez González, Alberto
author_facet Sánchez González, Alberto
Castro Martín, Ángel de
Todorovich, Elías
author_role author
author2 Castro Martín, Ángel de
Todorovich, Elías
author2_role author
author
dc.contributor.none.fl_str_mv Departamento de Tecnología Electrónica y de las Comunicaciones
Escuela Politécnica Superior
dc.subject.none.fl_str_mv Field programmable gate array
Fixed-point
Floating-point
Hardware-in-the-loop
Real-time emulation
Informática
topic Field programmable gate array
Fixed-point
Floating-point
Hardware-in-the-loop
Real-time emulation
Informática
description As the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques are being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable Gate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation step is reduced, the incremental values for the state variables are reduced proportionally, increasing the difference between the current value of the state variable and its increments. This difference can lead to numerical resolution issues when both magnitudes cannot be stored simultaneously in the state variable. FPGA-based HIL systems generally use 32-bit floating-point due to hardware and timing restrictions but they may suffer from these resolution problems. This paper explores the limits of 32-bit floating-point arithmetics in the context of hardware-in-the-loop systems, and how a larger format can be used to avoid resolution problems. The consequences in terms of hardware resources and running frequency are also explored. Although the conclusions reached in this work can be applied to any digital device, they can be directly used in the field of FPGAs, where the designer can easily use custom floating-point arithmetics.
publishDate 2018
dc.date.none.fl_str_mv 2018
2018-09-27
dc.type.none.fl_str_mv research article
http://purl.org/coar/resource_type/c_2df8fbb1
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/10486/686680
https://dx.doi.org/10.3390/electronics7100219
url http://hdl.handle.net/10486/686680
https://dx.doi.org/10.3390/electronics7100219
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv MDPI (Basel, Switzerland)
publisher.none.fl_str_mv MDPI (Basel, Switzerland)
dc.source.none.fl_str_mv reponame:Biblos-e Archivo. Repositorio Institucional de la UAM
instname:Universidad Autónoma de Madrid
instname_str Universidad Autónoma de Madrid
reponame_str Biblos-e Archivo. Repositorio Institucional de la UAM
collection Biblos-e Archivo. Repositorio Institucional de la UAM
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300724

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