Análisis y evaluación de prestaciones del empleo de técnicas de caché para acelerar el proceso de búsqueda en tablas de páginas
[EN] The process of translate virtual adresses to physical addresses made by the processor's MMU requires multiple memory acceses to retrieve the input of each of the levels of the tree in the page table structure. The TLBs (Translaton Lookaside Buffers) avoids these accesses storing the ad...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2014 |
| País: | España |
| Institución: | Universitat Politècnica de València (UPV) |
| Repositorio: | RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia |
| Idioma: | español |
| OAI Identifier: | oai:riunet.upv.es:10251/56684 |
| Acceso en línea: | https://riunet.upv.es/handle/10251/56684 |
| Access Level: | acceso abierto |
| Palabra clave: | TLB MMU PTWC compartida Caché Memoria virtual Shared PTWC Virtual Memory ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES Máster Universitario en Ingeniería de Computadores-Màster Universitari en Enginyeria de Computadors |
| Sumario: | [EN] The process of translate virtual adresses to physical addresses made by the processor's MMU requires multiple memory acceses to retrieve the input of each of the levels of the tree in the page table structure. The TLBs (Translaton Lookaside Buffers) avoids these accesses storing the addresses of pages that have been translated more recently. However, whenever the TLB have a failure, is required complete the entire translation procces accesing multiple times to the page table in memory. The translation process was initially supported by software via the OS (exception handler made by each TLB miss), which greatly slowed the resolution of TLB misses. Fortunately, current processor have hardware support for the translation proccess by an automata called Page Table Walker, which is responsible to access in memory to each translation levels of page table. However, each of these memory accesses involves high latency compared to the access in cache levels, which appear increagsenly faster in relative terms. An effective way to acelerate this translation process is introduce a cache whitin (or near) to the MMU to store partial translations corresponding to each of translation levles of the page tables. Current proposal in this regard show the advantages to use the Page Table Walk Cache (PTWC) in each core. In this paper, in adittion to analyzing these adavantges employment settings of a shared PTWC configuration among dofferent cores make up the CMP. This analysis attemps to show the advantages of using a shared PTWC versus private PTWC |
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