Alternate test of LNAs through ensemble learning of on-chip digital envelope signatures
This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitiv...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión enviada para evaluación y publicación |
| Fecha de publicación: | 2011 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/66491 |
| Acceso en línea: | http://hdl.handle.net/11441/66491 https://doi.org/10.1007/s10836-010-5193-4 |
| Access Level: | acceso abierto |
| Sumario: | This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. A new Figure of Merit (FOM) is proposed to evaluate the prediction accuracy of the statistical model, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445 GHz low-power LNA and a simple envelope detector, and has been developed in a 90 nm CMOS technology. Post-layout simulations are provided to verify the functionality of the proposed test technique. |
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