A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have de...

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Detalles Bibliográficos
Autores: Clemente Barreira, Juan Antonio, Resano, Javier, González Calvo, Carlos, Mozos Muñoz, Daniel
Tipo de recurso: artículo
Fecha de publicación:2011
País:España
Institución:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/45146
Acceso en línea:https://hdl.handle.net/20.500.14352/45146
Access Level:acceso abierto
Palabra clave:004.312
Field Programmable Gate Arrays
Reconfigurable Architectures
Task scheduling
Hardware
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spelling A Hardware Implementation of a Run-Time Scheduler for Reconfigurable SystemsClemente Barreira, Juan AntonioResano, JavierGonzález Calvo, CarlosMozos Muñoz, Daniel004.312Field Programmable Gate ArraysReconfigurable ArchitecturesTask schedulingHardwareNew generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on As-Soon-As-Possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.IEEEUniversidad Complutense de Madrid20112011-07-0120112011-07-01journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/20.500.14352/45146reponame:Docta Complutenseinstname:Universidad Complutense de Madrid (UCM)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:docta.ucm.es:20.500.14352/451462026-06-02T12:44:21Z
dc.title.none.fl_str_mv A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
title A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
spellingShingle A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
Clemente Barreira, Juan Antonio
004.312
Field Programmable Gate Arrays
Reconfigurable Architectures
Task scheduling
Hardware
title_short A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
title_full A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
title_fullStr A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
title_full_unstemmed A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
title_sort A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
dc.creator.none.fl_str_mv Clemente Barreira, Juan Antonio
Resano, Javier
González Calvo, Carlos
Mozos Muñoz, Daniel
author Clemente Barreira, Juan Antonio
author_facet Clemente Barreira, Juan Antonio
Resano, Javier
González Calvo, Carlos
Mozos Muñoz, Daniel
author_role author
author2 Resano, Javier
González Calvo, Carlos
Mozos Muñoz, Daniel
author2_role author
author
author
dc.contributor.none.fl_str_mv Universidad Complutense de Madrid
dc.subject.none.fl_str_mv 004.312
Field Programmable Gate Arrays
Reconfigurable Architectures
Task scheduling
Hardware
topic 004.312
Field Programmable Gate Arrays
Reconfigurable Architectures
Task scheduling
Hardware
description New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on As-Soon-As-Possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.
publishDate 2011
dc.date.none.fl_str_mv 2011
2011-07-01
2011
2011-07-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/20.500.14352/45146
url https://hdl.handle.net/20.500.14352/45146
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv IEEE
publisher.none.fl_str_mv IEEE
dc.source.none.fl_str_mv reponame:Docta Complutense
instname:Universidad Complutense de Madrid (UCM)
instname_str Universidad Complutense de Madrid (UCM)
reponame_str Docta Complutense
collection Docta Complutense
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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