Systolic implementation for deconvolution iterative algorithm
Systolic architectures implement regular algorithms in hardware, in order to obtain high computational throughput. In this paper we provide a modular architecture for a deconvolution iterative algorithm. The basic module is a systolic array which implement one iteration of the algorithm recentley pr...
| Autores: | , |
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| Tipo de documento: | relatório científico |
| Data de publicação: | 1985 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositório: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglês |
| OAI Identifier: | oai:upcommons.upc.edu:2117/110915 |
| Acesso em linha: | https://hdl.handle.net/2117/110915 |
| Access Level: | Acceso aberto |
| Palavra-chave: | Systolic array circuits Parallel processing (Electronic computers) Processament en paral·lel (Ordinadors) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
| Resumo: | Systolic architectures implement regular algorithms in hardware, in order to obtain high computational throughput. In this paper we provide a modular architecture for a deconvolution iterative algorithm. The basic module is a systolic array which implement one iteration of the algorithm recentley proposed in 1. The algorithm is a generalization of the method to invert non singular polynomial transfer function, previously publoshed in 2. The basic systoloc module can be repeteadly concatenated in such a way that can be used in real time applications. |
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