In-memory-computing CNN accelerator employing charge-domain compute
High-dimensional matrix-vector-multiplications (MVM) are the main operations of deep neural networks (DNN). As the size of DNNs increases, data movement becomes a problem and limits their performance. Analog in-memory computing accelerators are one of the most promising solutions to reduce this prob...
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| Formato: | tesis de maestría |
| Fecha de publicación: | 2020 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/340559 |
| Acesso em linha: | https://hdl.handle.net/2117/340559 |
| Access Level: | acceso abierto |
| Palavra-chave: | Neural networks (Computer science) Energy consumption AI ML DL NN CNN SRAM Xarxes neuronals (Informàtica) Energia -- Consum Àrees temàtiques de la UPC::Enginyeria electrònica |
| Resumo: | High-dimensional matrix-vector-multiplications (MVM) are the main operations of deep neural networks (DNN). As the size of DNNs increases, data movement becomes a problem and limits their performance. Analog in-memory computing accelerators are one of the most promising solutions to reduce this problem. This project designs an in-memory computing solution that employs charge-domain compute using 22FDX technology. The design, called multiplying bit cell (M-BC), consists of an 8T bit cell and a MOM capacitor. The design is part of an architecture of 8x8 = 64 neuron tiles that performs the filtering operation of up to 3x3x512 input activation (IA). Each neuron tile is composed of 64x64 = 4096 neuron patches. The design achieves energy efficiency of 1170 TOPS/W and throughput of 18876 GOPS. |
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