Memristive logic in crossbar memory arrays: Variability-aware design for higher reliability
© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to se...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2019 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/168773 |
| Acceso en línea: | https://hdl.handle.net/2117/168773 https://dx.doi.org/10.1109/TNANO.2019.2923731 |
| Access Level: | acceso abierto |
| Palabra clave: | Integrated circuits Transistors Memristor MAGIC CNIMP IMPLY Ratioed logic In-memory computing Resistive switching Crossbar array Circuits integrats Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors |
| Sumario: | © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
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