Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters

This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation is used for the current reference tracking of...

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Detalles Bibliográficos
Autores: Zafra Ratia, Eduardo, Vázquez Pérez, Sergio, Guzmán-Miranda, Hipólito, Sánchez Segura, Juan Antonio, Márquez Alcaide, Abraham, León Galván, José Ignacio, García Franquelo, Leopoldo
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2020
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/98699
Acceso en línea:https://hdl.handle.net/11441/98699
https://doi.org/10.3390/en13051074
Access Level:acceso abierto
Palabra clave:Field-programmable gate array (FPGA)
Field-programmable system-on-chip (FPSoC)
Finite control set (FCS)
Model predictive control (MPC)
Voltage source inverter (VSI)
Descripción
Sumario:This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation is used for the current reference tracking of a two-level three-phase power converter. The proposed solution is an enabler for using both complex control algorithms and digital controllers for high switching frequency semiconductor technologies. An original HW/SW (hardware and software) system architecture for an FPSoC is designed to take advantage of a modern operating system, while removing time uncertainty in real-time software tasks, and exploiting dedicated FPGA fabric for the most complex computations. In addition, two different architectures for the FPGA-implemented functionality are proposed and compared in order to study the area-speed trade-off. Experimental results show the feasibility of the proposed implementation, which achieves a speed hundreds of times faster than the conventional Digital Signal Processor (DSP)-based control platform.