Impact of the noise on the emulated grid voltage signal in hardware-in-the-loop used in power converters
This work evaluates the impact of the input voltage noise on a Hardware-In-the-Loop (HIL) system used in the emulation of power converters. A poor signal-to-noise ratio (SNR) can compromise the accuracy and precision of the model, and even make certain techniques for building mathematical models unf...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2023 |
| País: | España |
| Institución: | Universidad de Cantabria (UC) |
| Repositorio: | UCrea Repositorio Abierto de la Universidad de Cantabria |
| Idioma: | inglés |
| OAI Identifier: | oai:repositorio.unican.es:10902/27963 |
| Acceso en línea: | https://hdl.handle.net/10902/27963 |
| Access Level: | acceso abierto |
| Palabra clave: | Hardware-in-the-loop HIL Power converter Noise Error sources ADC |
| Sumario: | This work evaluates the impact of the input voltage noise on a Hardware-In-the-Loop (HIL) system used in the emulation of power converters. A poor signal-to-noise ratio (SNR) can compromise the accuracy and precision of the model, and even make certain techniques for building mathematical models unfeasible. The case study presents the noise effects on a digitally controlled totem-pole converter emulated with a low-cost HIL system using an FPGA. The effects on the model outputs, and the cost and influence of different hardware implementations, are evaluated. The noise of the input signals may limit the benefits of increasing the resolution of the model. |
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