Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC

The use of deep learning solutions in different disciplines is increasing and their algorithms are computationally expensive in most cases. For this reason, numerous hardware accelerators have appeared to compute their operations efficiently in parallel, achieving higher performance and lower latenc...

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Autores: Ríos Navarro, José Antonio, Gutiérrez Galán, Daniel, Domínguez Morales, Juan Pedro, Piñero-Fuentes, Enrique, Durán López, Lourdes, Tapiador Morales, Ricardo, Domínguez Morales, Manuel Jesús
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2021
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/112503
Acceso en línea:https://hdl.handle.net/11441/112503
https://doi.org/10.3390/electronics10010094
Access Level:acceso abierto
Palabra clave:Deep learning
Embedded systems
PSoC
Memory organization
FPGA
Hardware accelerator
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spelling Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoCRíos Navarro, José AntonioGutiérrez Galán, DanielDomínguez Morales, Juan PedroPiñero-Fuentes, EnriqueDurán López, LourdesTapiador Morales, RicardoDomínguez Morales, Manuel JesúsDeep learningEmbedded systemsPSoCMemory organizationFPGAHardware acceleratorThe use of deep learning solutions in different disciplines is increasing and their algorithms are computationally expensive in most cases. For this reason, numerous hardware accelerators have appeared to compute their operations efficiently in parallel, achieving higher performance and lower latency. These algorithms need large amounts of data to feed each of their computing layers, which makes it necessary to efficiently handle the data transfers that feed and collect the information to and from the accelerators. For the implementation of these accelerators, hybrid devices are widely used, which have an embedded computer, where an operating system can be run, and a field-programmable gate array (FPGA), where the accelerator can be deployed. In this work, we present a software API that efficiently organizes the memory, preventing reallocating data from one memory area to another, which improves the native Linux driver with a 85% speed-up and reduces the frame computing time by 28% in a real application.Spanish Agencia Estatal de Investigación (AEI) project MINDROB: “Percepción y Cognición Neuromórfica para Actuación Robótica de Alta Velocidad PID2019- 105556GB-C33Spanish Agencia Estatal de Investigación (AEI) project MINDROB: “Percepción y Cognición Neuromórfica para Actuación Robótica de Alta Velocidad AEI/10.13039/501100011033MDPIArquitectura y Tecnología de ComputadoresTEP108: Robótica y Tecnología de Computadores2021info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/112503https://doi.org/10.3390/electronics10010094reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésElectonics, 10 (1), 94-.PID2019- 105556GB-C33AEI/10.13039/501100011033https://www.mdpi.com/2079-9292/10/1/94info:eu-repo/semantics/openAccessoai:idus.us.es:11441/1125032026-06-17T12:51:07Z
dc.title.none.fl_str_mv Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
title Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
spellingShingle Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
Ríos Navarro, José Antonio
Deep learning
Embedded systems
PSoC
Memory organization
FPGA
Hardware accelerator
title_short Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
title_full Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
title_fullStr Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
title_full_unstemmed Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
title_sort Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
dc.creator.none.fl_str_mv Ríos Navarro, José Antonio
Gutiérrez Galán, Daniel
Domínguez Morales, Juan Pedro
Piñero-Fuentes, Enrique
Durán López, Lourdes
Tapiador Morales, Ricardo
Domínguez Morales, Manuel Jesús
author Ríos Navarro, José Antonio
author_facet Ríos Navarro, José Antonio
Gutiérrez Galán, Daniel
Domínguez Morales, Juan Pedro
Piñero-Fuentes, Enrique
Durán López, Lourdes
Tapiador Morales, Ricardo
Domínguez Morales, Manuel Jesús
author_role author
author2 Gutiérrez Galán, Daniel
Domínguez Morales, Juan Pedro
Piñero-Fuentes, Enrique
Durán López, Lourdes
Tapiador Morales, Ricardo
Domínguez Morales, Manuel Jesús
author2_role author
author
author
author
author
author
dc.contributor.none.fl_str_mv Arquitectura y Tecnología de Computadores
TEP108: Robótica y Tecnología de Computadores
dc.subject.none.fl_str_mv Deep learning
Embedded systems
PSoC
Memory organization
FPGA
Hardware accelerator
topic Deep learning
Embedded systems
PSoC
Memory organization
FPGA
Hardware accelerator
description The use of deep learning solutions in different disciplines is increasing and their algorithms are computationally expensive in most cases. For this reason, numerous hardware accelerators have appeared to compute their operations efficiently in parallel, achieving higher performance and lower latency. These algorithms need large amounts of data to feed each of their computing layers, which makes it necessary to efficiently handle the data transfers that feed and collect the information to and from the accelerators. For the implementation of these accelerators, hybrid devices are widely used, which have an embedded computer, where an operating system can be run, and a field-programmable gate array (FPGA), where the accelerator can be deployed. In this work, we present a software API that efficiently organizes the memory, preventing reallocating data from one memory area to another, which improves the native Linux driver with a 85% speed-up and reduces the frame computing time by 28% in a real application.
publishDate 2021
dc.date.none.fl_str_mv 2021
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/112503
https://doi.org/10.3390/electronics10010094
url https://hdl.handle.net/11441/112503
https://doi.org/10.3390/electronics10010094
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Electonics, 10 (1), 94-.
PID2019- 105556GB-C33
AEI/10.13039/501100011033
https://www.mdpi.com/2079-9292/10/1/94
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv MDPI
publisher.none.fl_str_mv MDPI
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.300724

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