Hardware/software solutions to enable the use of high-performance processors in the most stringent safety-critical systems
(English) Future Safety-Critical Systems require a boost in guaranteed performance in order to satisfy the increasing performance demands of the state-of-the-art complex software features. Ar1 approach to achieve these performance requirements is the usage of High-Performance Computing (HPC) compone...
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| Tipo de recurso: | tesis doctoral |
| Estado: | Versión publicada |
| Fecha de publicación: | 2023 |
| País: | España |
| Institución: | CBUC, CESCA |
| Repositorio: | TDR. Tesis Doctorales en Red |
| OAI Identifier: | oai:www.tdx.cat:10803/690103 |
| Acceso en línea: | http://hdl.handle.net/10803/690103 https://dx.doi.org/10.5821/dissertation-2117-402844 |
| Access Level: | acceso abierto |
| Palabra clave: | Àrees temàtiques de la UPC::Informàtica 004 |
| Sumario: | (English) Future Safety-Critical Systems require a boost in guaranteed performance in order to satisfy the increasing performance demands of the state-of-the-art complex software features. Ar1 approach to achieve these performance requirements is the usage of High-Performance Computing (HPC) components which can deliver more computation power than current safety critical components. However, the dependability support of these HPC components are not the same as that for the safety- critical components, so HPC components can jeopardize the functional safety of the entire system, especially since some of the highest-criticality functionalities maybe executed entirely on top of these components (e.g., neural networks in a Graphical Processing Unit (GPU)). Based on the safety requirements of performance-hungry critical applications, such as those for an autonomous operation, these HPC components must comply with the highest criticality levels, hence including the required dependability support. The overarching goal of this thesis is to present techniques to achieve that in different HPC components. In particular, we focus on GPUs and multicores. The techniques presented aim at providing diverse redundant execution, as needed to avoid Common Cause Failure (CCF)s, which are those defeating safety measures (e.g., pure redundancy) as a consequence of a single-point fault (e.g., a fault affecting both redundant instances identically). Such a solution is comparable to the lockstep execution employed on safety-critical processors. The first set of contributions of this thesis focuses on enabling diverse redundant execution on a single GPU. We propose two different solutions: (1) a slight hardware modification affecting the internal scheduler of the GPU and (2) a software-only approach that requires knowledge of the hardware resources of the GPU. In these contributions, we also analyze the staggering created due to the CPU-GPU inherent interaction. Finally, the last contribution relates to multicore systems. Similarly to the previous contributions, we focused on enabling diverse redundant execution on this component. However, executing a workload twice in two different cores is something relatively simple with modern programming models (e.g., OpenMP, OpenMPI). The real challenge is in using the limited observability and controllabilitychannels to maintain and guarantee the (time) diversity between these two redundant executions, like the lockstep approach. Note that lockstep is an expensive approach that hijacks halfofthe cores, which are non-visible to the user and cannot be used for non-critical applications. Instead, if a flexible software-only solution for COTS multicores existed, all cores could be used by non-critical applications when not needed for the safety-critical ones. Thus, maximizing their utilization. To tackle this challenge, we proposed a software-only solution with small requirements that can be met by most existing COTS multicore. |
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