Predictable performance in SMT processors: synergy between the OS and SMTs

Current operating systems (OS) perceive the different contexts of simultaneous multithreaded (SMT) processors as multiple independent processing units, although, in reality, threads executed in these units compete for the same hardware resources. Furthermore, hardware resources are assigned to threa...

Descripción completa

Detalles Bibliográficos
Autores: Cazorla, Francisco, Knijnenburg, Peter M.W., Sakellariou, Rizos, Fernandez Prieto, Enrique, Ramírez Bellido, Alejandro, Valero Cortés, Mateo|||0000-0003-2917-2482
Tipo de recurso: artículo
Fecha de publicación:2006
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/105885
Acceso en línea:https://hdl.handle.net/2117/105885
https://dx.doi.org/10.1109/TC.2006.108
Access Level:acceso abierto
Palabra clave:Operating systems (Computers)
Simultaneous multithreading processors
Embedded computer systems
Multithreaded processors
Simultaneous multithreading
ILP
Thread-level parallelism
Performance predictability
Real time
Operating systems
Sistemes operatius (Ordinadors)
Ordinadors immersos, Sistemes d'
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
id ES_aeac2e609641d2567bab8b87f0234a8a
oai_identifier_str oai:upcommons.upc.edu:2117/105885
network_acronym_str ES
network_name_str España
repository_id_str
spelling Predictable performance in SMT processors: synergy between the OS and SMTsCazorla, FranciscoKnijnenburg, Peter M.W.Sakellariou, RizosFernandez Prieto, EnriqueRamírez Bellido, AlejandroValero Cortés, Mateo|||0000-0003-2917-2482Operating systems (Computers)Simultaneous multithreading processorsEmbedded computer systemsMultithreaded processorsSimultaneous multithreadingILPThread-level parallelismPerformance predictabilityReal timeOperating systemsSistemes operatius (Ordinadors)Ordinadors immersos, Sistemes d'Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadorsCurrent operating systems (OS) perceive the different contexts of simultaneous multithreaded (SMT) processors as multiple independent processing units, although, in reality, threads executed in these units compete for the same hardware resources. Furthermore, hardware resources are assigned to threads implicitly as determined by the SMT instruction fetch (Ifetch) policy, without the control of the OS. Both factors cause a lack of control over how individual threads are executed, which can frustrate the work of the job scheduler. This presents a problem for general purpose systems, where the OS job scheduler cannot enforce priorities, and also for embedded systems, where it would be difficult to guarantee worst-case execution times. In this paper, we propose a novel strategy that enables a two-way interaction between the OS and the SMT processor and allows the OS to run jobs at a certain percentage of their maximum speed, regardless of the workload in which these jobs are executed. In contrast to previous approaches, our approach enables the OS to run time-critical jobs without dedicating all internal resources to them so that non-time-critical jobs can make significant progress as well and without significantly compromising overall throughput. In fact, our mechanism, in addition to fulfilling OS requirements, achieves 90 percent of the throughput of one of the best currently known fetch policies for SMTs.Peer Reviewed20062006-07-0120172017-06-27journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/105885https://dx.doi.org/10.1109/TC.2006.108reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/1058852026-05-27T15:37:01Z
dc.title.none.fl_str_mv Predictable performance in SMT processors: synergy between the OS and SMTs
title Predictable performance in SMT processors: synergy between the OS and SMTs
spellingShingle Predictable performance in SMT processors: synergy between the OS and SMTs
Cazorla, Francisco
Operating systems (Computers)
Simultaneous multithreading processors
Embedded computer systems
Multithreaded processors
Simultaneous multithreading
ILP
Thread-level parallelism
Performance predictability
Real time
Operating systems
Sistemes operatius (Ordinadors)
Ordinadors immersos, Sistemes d'
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
title_short Predictable performance in SMT processors: synergy between the OS and SMTs
title_full Predictable performance in SMT processors: synergy between the OS and SMTs
title_fullStr Predictable performance in SMT processors: synergy between the OS and SMTs
title_full_unstemmed Predictable performance in SMT processors: synergy between the OS and SMTs
title_sort Predictable performance in SMT processors: synergy between the OS and SMTs
dc.creator.none.fl_str_mv Cazorla, Francisco
Knijnenburg, Peter M.W.
Sakellariou, Rizos
Fernandez Prieto, Enrique
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author Cazorla, Francisco
author_facet Cazorla, Francisco
Knijnenburg, Peter M.W.
Sakellariou, Rizos
Fernandez Prieto, Enrique
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author_role author
author2 Knijnenburg, Peter M.W.
Sakellariou, Rizos
Fernandez Prieto, Enrique
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author2_role author
author
author
author
author
dc.subject.none.fl_str_mv Operating systems (Computers)
Simultaneous multithreading processors
Embedded computer systems
Multithreaded processors
Simultaneous multithreading
ILP
Thread-level parallelism
Performance predictability
Real time
Operating systems
Sistemes operatius (Ordinadors)
Ordinadors immersos, Sistemes d'
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
topic Operating systems (Computers)
Simultaneous multithreading processors
Embedded computer systems
Multithreaded processors
Simultaneous multithreading
ILP
Thread-level parallelism
Performance predictability
Real time
Operating systems
Sistemes operatius (Ordinadors)
Ordinadors immersos, Sistemes d'
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
description Current operating systems (OS) perceive the different contexts of simultaneous multithreaded (SMT) processors as multiple independent processing units, although, in reality, threads executed in these units compete for the same hardware resources. Furthermore, hardware resources are assigned to threads implicitly as determined by the SMT instruction fetch (Ifetch) policy, without the control of the OS. Both factors cause a lack of control over how individual threads are executed, which can frustrate the work of the job scheduler. This presents a problem for general purpose systems, where the OS job scheduler cannot enforce priorities, and also for embedded systems, where it would be difficult to guarantee worst-case execution times. In this paper, we propose a novel strategy that enables a two-way interaction between the OS and the SMT processor and allows the OS to run jobs at a certain percentage of their maximum speed, regardless of the workload in which these jobs are executed. In contrast to previous approaches, our approach enables the OS to run time-critical jobs without dedicating all internal resources to them so that non-time-critical jobs can make significant progress as well and without significantly compromising overall throughput. In fact, our mechanism, in addition to fulfilling OS requirements, achieves 90 percent of the throughput of one of the best currently known fetch policies for SMTs.
publishDate 2006
dc.date.none.fl_str_mv 2006
2006-07-01
2017
2017-06-27
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/105885
https://dx.doi.org/10.1109/TC.2006.108
url https://hdl.handle.net/2117/105885
https://dx.doi.org/10.1109/TC.2006.108
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869416600412618752
score 15,300719

Similares en LA Referencia