A Multi-Self-Cascoded Voltage Reference with 2.73-ppm/V Line Sensitivity and 20.1-ppm/°C Temperature Coefficient at 0.45-V Supply
Recent advancements in low-power and low-voltage integrated circuits have spurred significant research interest, particularly for applications with demanding supply conditions. This work presents a single-branch voltage reference achieving exceptional immunity to supply voltage variations. Leveragin...
| Autores: | , , , , |
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| Tipo de recurso: | capítulo de libro |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Autònoma de Barcelona |
| Repositorio: | Dipòsit Digital de Documents de la UAB |
| Idioma: | inglés |
| OAI Identifier: | oai:dnet:uabarcelona_::00ecbd9f1369c8de8b230599825105f9 |
| Acceso en línea: | https://ddd.uab.cat/record/326648 https://dx.doi.org/urn:doi:10.1109/MWSCAS53549.2025.11244514 |
| Access Level: | acceso abierto |
| Palabra clave: | Voltage reference Low power Low voltage Energy harvesting Temperature coefficient Line sensitivity PSRR Selfcascoded Reverse short-channel effect Temperature sensors Semiconductor device modeling Integrated circuits Power demand Circuits and systems Threshold voltage Transistors |
| Sumario: | Recent advancements in low-power and low-voltage integrated circuits have spurred significant research interest, particularly for applications with demanding supply conditions. This work presents a single-branch voltage reference achieving exceptional immunity to supply voltage variations. Leveraging a Δ V-based approach, the design utilizes transistors with different channel lengths to exploit geometry-dependent threshold voltage differences, enabling effective temperature compensation. Additionally, a multi-self-cascoded technique enhances immunity to supply voltage variations. Post-layout simulations of a 0.18 μ m CMOS design, operating with supply voltage as low as 0.45 V, demonstrate a line sensitivity of 2.73 ppm/V and a temperature coefficient of 20.1 ppm/°C, with power consumption below 200 pW. The proposed architecture is shown to be a robust solution for implementing precise, low-voltage and low-power voltage references. |
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